projects / openwrt / openwrt.git / blob
? search:


870bcb8d7ab67091c3429cb979e0dc690bd5bce9
[openwrt/openwrt.git] /
1 From d3feb406733544dbf0e239ef945a09decdceac88 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
3 Date: Thu, 14 Apr 2016 11:37:43 +0200
4 Subject: [PATCH] phy: bcm-ns-usb2: new driver for USB 2.0 PHY on Northstar
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 Northstar is a family of SoCs used in home routers. They have USB 2.0
10 and 3.0 controllers with PHYs that need to be properly initialized.
11 This driver provides PHY init support in a generic way and can be bound
12 with an EHCI controller driver.
13 There are (just a few) registers being defined in bcma header. It's
14 because DMU/CRU registers will be also needed in other drivers. We will
15 need them e.g. in PCIe controller/PHY driver and at some point probably
16 in clock driver for BCM53573 chipset. By using include/linux/bcma/ we
17 avoid code duplication.
18
19 Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
20 Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
21 ---
22 .../devicetree/bindings/phy/bcm-ns-usb2-phy.txt | 21 ++++
23 drivers/phy/Kconfig | 9 ++
24 drivers/phy/Makefile | 1 +
25 drivers/phy/phy-bcm-ns-usb2.c | 137 +++++++++++++++++++++
26 include/linux/bcma/bcma.h | 1 +
27 include/linux/bcma/bcma_driver_arm_c9.h | 15 +++
28 6 files changed, 184 insertions(+)
29 create mode 100644 Documentation/devicetree/bindings/phy/bcm-ns-usb2-phy.txt
30 create mode 100644 drivers/phy/phy-bcm-ns-usb2.c
31 create mode 100644 include/linux/bcma/bcma_driver_arm_c9.h
32
33 diff --git a/Documentation/devicetree/bindings/phy/bcm-ns-usb2-phy.txt b/Documentation/devicetree/bindings/phy/bcm-ns-usb2-phy.txt
34 new file mode 100644
35 index 0000000..a7aee9e
36 --- /dev/null
37 +++ b/Documentation/devicetree/bindings/phy/bcm-ns-usb2-phy.txt
38 @@ -0,0 +1,21 @@
39 +Driver for Broadcom Northstar USB 2.0 PHY
40 +
41 +Required properties:
42 +- compatible: brcm,ns-usb2-phy
43 +- reg: iomem address range of DMU (Device Management Unit)
44 +- reg-names: "dmu", the only needed & supported reg right now
45 +- clocks: USB PHY reference clock
46 +- clock-names: "phy-ref-clk", the only needed & supported clock right now
47 +
48 +To initialize USB 2.0 PHY driver needs to setup PLL correctly. To do this it
49 +requires passing phandle to the USB PHY reference clock.
50 +
51 +Example:
52 + usb2-phy {
53 + compatible = "brcm,ns-usb2-phy";
54 + reg = <0x1800c000 0x1000>;
55 + reg-names = "dmu";
56 + #phy-cells = <0>;
57 + clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
58 + clock-names = "phy-ref-clk";
59 + };
60 diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
61 index f6ff76e..f2b458f 100644
62 --- a/drivers/phy/Kconfig
63 +++ b/drivers/phy/Kconfig
64 @@ -15,6 +15,15 @@ config GENERIC_PHY
65 phy users can obtain reference to the PHY. All the users of this
66 framework should select this config.
67
68 +config PHY_BCM_NS_USB2
69 + tristate "Broadcom Northstar USB 2.0 PHY Driver"
70 + depends on ARCH_BCM_IPROC || COMPILE_TEST
71 + depends on HAS_IOMEM && OF
72 + select GENERIC_PHY
73 + help
74 + Enable this to support Broadcom USB 2.0 PHY connected to the USB
75 + controller on Northstar family.
76 +
77 config PHY_BERLIN_USB
78 tristate "Marvell Berlin USB PHY Driver"
79 depends on ARCH_BERLIN && RESET_CONTROLLER && HAS_IOMEM && OF
80 diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
81 index f03fa1f..0de09e1 100644
82 --- a/drivers/phy/Makefile
83 +++ b/drivers/phy/Makefile
84 @@ -3,6 +3,7 @@
85 #
86
87 obj-$(CONFIG_GENERIC_PHY) += phy-core.o
88 +obj-$(CONFIG_PHY_BCM_NS_USB2) += phy-bcm-ns-usb2.o
89 obj-$(CONFIG_PHY_BERLIN_USB) += phy-berlin-usb.o
90 obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o
91 obj-$(CONFIG_PHY_DM816X_USB) += phy-dm816x-usb.o
92 diff --git a/drivers/phy/phy-bcm-ns-usb2.c b/drivers/phy/phy-bcm-ns-usb2.c
93 new file mode 100644
94 index 0000000..95ab6b2
95 --- /dev/null
96 +++ b/drivers/phy/phy-bcm-ns-usb2.c
97 @@ -0,0 +1,137 @@
98 +/*
99 + * Broadcom Northstar USB 2.0 PHY Driver
100 + *
101 + * Copyright (C) 2016 Rafał Miłecki <zajec5@gmail.com>
102 + *
103 + * This program is free software; you can redistribute it and/or modify
104 + * it under the terms of the GNU General Public License version 2 as
105 + * published by the Free Software Foundation.
106 + *
107 + */
108 +
109 +#include <linux/bcma/bcma.h>
110 +#include <linux/clk.h>
111 +#include <linux/delay.h>
112 +#include <linux/err.h>
113 +#include <linux/module.h>
114 +#include <linux/of_address.h>
115 +#include <linux/of_platform.h>
116 +#include <linux/phy/phy.h>
117 +#include <linux/platform_device.h>
118 +#include <linux/slab.h>
119 +
120 +struct bcm_ns_usb2 {
121 + struct device *dev;
122 + struct clk *ref_clk;
123 + struct phy *phy;
124 + void __iomem *dmu;
125 +};
126 +
127 +static int bcm_ns_usb2_phy_init(struct phy *phy)
128 +{
129 + struct bcm_ns_usb2 *usb2 = phy_get_drvdata(phy);
130 + struct device *dev = usb2->dev;
131 + void __iomem *dmu = usb2->dmu;
132 + u32 ref_clk_rate, usb2ctl, usb_pll_ndiv, usb_pll_pdiv;
133 + int err = 0;
134 +
135 + err = clk_prepare_enable(usb2->ref_clk);
136 + if (err < 0) {
137 + dev_err(dev, "Failed to prepare ref clock: %d\n", err);
138 + goto err_out;
139 + }
140 +
141 + ref_clk_rate = clk_get_rate(usb2->ref_clk);
142 + if (!ref_clk_rate) {
143 + dev_err(dev, "Failed to get ref clock rate\n");
144 + err = -EINVAL;
145 + goto err_clk_off;
146 + }
147 +
148 + usb2ctl = readl(dmu + BCMA_DMU_CRU_USB2_CONTROL);
149 +
150 + if (usb2ctl & BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_MASK) {
151 + usb_pll_pdiv = usb2ctl;
152 + usb_pll_pdiv &= BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_MASK;
153 + usb_pll_pdiv >>= BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_SHIFT;
154 + } else {
155 + usb_pll_pdiv = 1 << 3;
156 + }
157 +
158 + /* Calculate ndiv based on a solid 1920 MHz that is for USB2 PHY */
159 + usb_pll_ndiv = (1920000000 * usb_pll_pdiv) / ref_clk_rate;
160 +
161 + /* Unlock DMU PLL settings with some magic value */
162 + writel(0x0000ea68, dmu + BCMA_DMU_CRU_CLKSET_KEY);
163 +
164 + /* Write USB 2.0 PLL control setting */
165 + usb2ctl &= ~BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_MASK;
166 + usb2ctl |= usb_pll_ndiv << BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_SHIFT;
167 + writel(usb2ctl, dmu + BCMA_DMU_CRU_USB2_CONTROL);
168 +
169 + /* Lock DMU PLL settings */
170 + writel(0x00000000, dmu + BCMA_DMU_CRU_CLKSET_KEY);
171 +
172 +err_clk_off:
173 + clk_disable_unprepare(usb2->ref_clk);
174 +err_out:
175 + return err;
176 +}
177 +
178 +static const struct phy_ops ops = {
179 + .init = bcm_ns_usb2_phy_init,
180 + .owner = THIS_MODULE,
181 +};
182 +
183 +static int bcm_ns_usb2_probe(struct platform_device *pdev)
184 +{
185 + struct device *dev = &pdev->dev;
186 + struct bcm_ns_usb2 *usb2;
187 + struct resource *res;
188 + struct phy_provider *phy_provider;
189 +
190 + usb2 = devm_kzalloc(&pdev->dev, sizeof(*usb2), GFP_KERNEL);
191 + if (!usb2)
192 + return -ENOMEM;
193 + usb2->dev = dev;
194 +
195 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dmu");
196 + usb2->dmu = devm_ioremap_resource(dev, res);
197 + if (IS_ERR(usb2->dmu)) {
198 + dev_err(dev, "Failed to map DMU regs\n");
199 + return PTR_ERR(usb2->dmu);
200 + }
201 +
202 + usb2->ref_clk = devm_clk_get(dev, "phy-ref-clk");
203 + if (IS_ERR(usb2->ref_clk)) {
204 + dev_err(dev, "Clock not defined\n");
205 + return PTR_ERR(usb2->ref_clk);
206 + }
207 +
208 + usb2->phy = devm_phy_create(dev, NULL, &ops);
209 + if (IS_ERR(dev))
210 + return PTR_ERR(dev);
211 +
212 + phy_set_drvdata(usb2->phy, usb2);
213 + platform_set_drvdata(pdev, usb2);
214 +
215 + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
216 + return PTR_ERR_OR_ZERO(phy_provider);
217 +}
218 +
219 +static const struct of_device_id bcm_ns_usb2_id_table[] = {
220 + { .compatible = "brcm,ns-usb2-phy", },
221 + {},
222 +};
223 +MODULE_DEVICE_TABLE(of, bcm_ns_usb2_id_table);
224 +
225 +static struct platform_driver bcm_ns_usb2_driver = {
226 + .probe = bcm_ns_usb2_probe,
227 + .driver = {
228 + .name = "bcm_ns_usb2",
229 + .of_match_table = bcm_ns_usb2_id_table,
230 + },
231 +};
232 +module_platform_driver(bcm_ns_usb2_driver);
233 +
234 +MODULE_LICENSE("GPL v2");
235 diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h
236 index 0367c63..e6b41f4 100644
237 --- a/include/linux/bcma/bcma.h
238 +++ b/include/linux/bcma/bcma.h
239 @@ -4,6 +4,7 @@
240 #include <linux/pci.h>
241 #include <linux/mod_devicetable.h>
242
243 +#include <linux/bcma/bcma_driver_arm_c9.h>
244 #include <linux/bcma/bcma_driver_chipcommon.h>
245 #include <linux/bcma/bcma_driver_pci.h>
246 #include <linux/bcma/bcma_driver_pcie2.h>
247 diff --git a/include/linux/bcma/bcma_driver_arm_c9.h b/include/linux/bcma/bcma_driver_arm_c9.h
248 new file mode 100644
249 index 0000000..93bd73d
250 --- /dev/null
251 +++ b/include/linux/bcma/bcma_driver_arm_c9.h
252 @@ -0,0 +1,15 @@
253 +#ifndef LINUX_BCMA_DRIVER_ARM_C9_H_
254 +#define LINUX_BCMA_DRIVER_ARM_C9_H_
255 +
256 +/* DMU (Device Management Unit) */
257 +#define BCMA_DMU_CRU_USB2_CONTROL 0x0164
258 +#define BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_MASK 0x00000FFC
259 +#define BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_SHIFT 2
260 +#define BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_MASK 0x00007000
261 +#define BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_SHIFT 12
262 +#define BCMA_DMU_CRU_CLKSET_KEY 0x0180
263 +#define BCMA_DMU_CRU_STRAPS_CTRL 0x02A0
264 +#define BCMA_DMU_CRU_STRAPS_CTRL_USB3 0x00000010
265 +#define BCMA_DMU_CRU_STRAPS_CTRL_4BYTE 0x00008000
266 +
267 +#endif /* LINUX_BCMA_DRIVER_ARM_C9_H_ */
268 --
269 1.8.4.5
270
OpenWrt Source Repository