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1 From 0c767bcfe1b4d940f2889820f12d278cbba764b5 Mon Sep 17 00:00:00 2001
2 From: Alex Marginean <alexandru.marginean@nxp.com>
3 Date: Tue, 27 Aug 2019 15:12:00 +0300
4 Subject: [PATCH] arm64: dts: ls1028a: define networking options for QDS
5
6 Defines connectivity for a few serdes protocol combinations (85xx, 65xx,
7 13xx, 9999, 7777).
8
9 Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
10 ---
11 .../boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi | 20 ++++++++
12 .../boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi | 20 ++++++++
13 .../boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi | 56 ++++++++++++++++++++
14 .../boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi | 19 +++++++
15 .../boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi | 60 ++++++++++++++++++++++
16 .../boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi | 48 +++++++++++++++++
17 .../boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi | 44 ++++++++++++++++
18 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 27 ++++++++++
19 8 files changed, 294 insertions(+)
20 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi
21 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi
22 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi
23 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi
24 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi
25 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi
26 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi
27
28 --- /dev/null
29 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi
30 @@ -0,0 +1,20 @@
31 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
32 +/*
33 + * Device Tree Include file for LS1028A QDS board, serdes 1xxx
34 + *
35 + * Copyright 2019 NXP
36 + *
37 + */
38 +
39 +&mdio_slot1 {
40 + slot1_sgmii: ethernet-phy@2 {
41 + /* AQR112 */
42 + reg = <0x2>;
43 + compatible = "ethernet-phy-ieee802.3-c45";
44 + };
45 +};
46 +
47 +&enetc_port0 {
48 + phy-handle = <&slot1_sgmii>;
49 + phy-connection-type = "usxgmii";
50 +};
51 --- /dev/null
52 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi
53 @@ -0,0 +1,20 @@
54 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
55 +/*
56 + * Device Tree Include file for LS1028A QDS board, serdes 6xxx
57 + *
58 + * Copyright 2019 NXP
59 + *
60 + */
61 +
62 +&mdio_slot1 {
63 + slot1_sgmii: ethernet-phy@2 {
64 + /* AQR112 */
65 + reg = <0x2>;
66 + compatible = "ethernet-phy-ieee802.3-c45";
67 + };
68 +};
69 +
70 +&enetc_port0 {
71 + phy-handle = <&slot1_sgmii>;
72 + phy-connection-type = "2500base-x";
73 +};
74 --- /dev/null
75 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi
76 @@ -0,0 +1,56 @@
77 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
78 +/*
79 + * Device Tree Include file for LS1028A QDS board, serdes 9999
80 + *
81 + * Copyright 2019 NXP
82 + *
83 + */
84 +
85 +&mdio_slot1 {
86 + /* two ports on AQR412 */
87 + slot1_sxgmii2: ethernet-phy@2 {
88 + reg = <0x2>;
89 + compatible = "ethernet-phy-ieee802.3-c45";
90 + };
91 + slot1_sxgmii3: ethernet-phy@3 {
92 + reg = <0x3>;
93 + compatible = "ethernet-phy-ieee802.3-c45";
94 + };
95 +};
96 +
97 +&mdio_slot2 {
98 + slot2_sxgmii0: ethernet-phy@2 {
99 + /* AQR112 */
100 + reg = <0x2>;
101 + compatible = "ethernet-phy-ieee802.3-c45";
102 + };
103 +};
104 +
105 +&mdio_slot3 {
106 + slot3_sxgmii0: ethernet-phy@2 {
107 + /* AQR112 */
108 + reg = <0x2>;
109 + compatible = "ethernet-phy-ieee802.3-c45";
110 + };
111 +};
112 +
113 +/* l2switch ports */
114 +&switch_port0 {
115 + phy-handle = <&slot1_sxgmii2>;
116 + phy-connection-type = "2500base-x";
117 +};
118 +
119 +&switch_port1 {
120 + phy-handle = <&slot2_sxgmii0>;
121 + phy-connection-type = "2500base-x";
122 +};
123 +
124 +&switch_port2 {
125 + phy-handle = <&slot3_sxgmii0>;
126 + phy-connection-type = "2500base-x";
127 +};
128 +
129 +&switch_port3 {
130 + phy-handle = <&slot1_sxgmii3>;
131 + phy-connection-type = "2500base-x";
132 +};
133 --- /dev/null
134 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi
135 @@ -0,0 +1,19 @@
136 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
137 +/*
138 + * Device Tree Include file for LS1028A QDS board, serdes 8xxx
139 + *
140 + * Copyright 2019 NXP
141 + *
142 + */
143 +
144 +&mdio_slot1 {
145 + slot1_sgmii: ethernet-phy@1c {
146 + /* 1st port on VSC8234 */
147 + reg = <0x1c>;
148 + };
149 +};
150 +
151 +&enetc_port0 {
152 + phy-handle = <&slot1_sgmii>;
153 + phy-connection-type = "sgmii";
154 +};
155 --- /dev/null
156 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi
157 @@ -0,0 +1,60 @@
158 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
159 +/*
160 + * Device Tree Include file for LS1028A QDS board, serdes 9999
161 + *
162 + * Copyright 2019 NXP
163 + *
164 + */
165 +
166 +&mdio_slot1 {
167 + /* VSC8234 */
168 + slot1_sgmii0: ethernet-phy@1c {
169 + reg = <0x1c>;
170 + };
171 + slot1_sgmii1: ethernet-phy@1d {
172 + reg = <0x1d>;
173 + };
174 + slot1_sgmii2: ethernet-phy@1e {
175 + reg = <0x1e>;
176 + };
177 + slot1_sgmii3: ethernet-phy@1f {
178 + reg = <0x1f>;
179 + };
180 +};
181 +
182 +&mdio_slot2 {
183 + /* VSC8234 */
184 + slot2_sgmii0: ethernet-phy@1c {
185 + reg = <0x1c>;
186 + };
187 + slot2_sgmii1: ethernet-phy@1d {
188 + reg = <0x1d>;
189 + };
190 + slot2_sgmii2: ethernet-phy@1e {
191 + reg = <0x1e>;
192 + };
193 + slot2_sgmii3: ethernet-phy@1f {
194 + reg = <0x1f>;
195 + };
196 +};
197 +
198 +/* l2switch ports */
199 +&switch_port0 {
200 + phy-handle = <&slot1_sgmii0>;
201 + phy-connection-type = "sgmii";
202 +};
203 +
204 +&switch_port1 {
205 + phy-handle = <&slot2_sgmii0>;
206 + phy-connection-type = "sgmii";
207 +};
208 +
209 +&switch_port2 {
210 + phy-handle = <&slot1_sgmii2>;
211 + phy-connection-type = "sgmii";
212 +};
213 +
214 +&switch_port3 {
215 + phy-handle = <&slot1_sgmii3>;
216 + phy-connection-type = "sgmii";
217 +};
218 --- /dev/null
219 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi
220 @@ -0,0 +1,48 @@
221 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
222 +/*
223 + * Device Tree Include file for LS1028A QDS board, serdes x3xx
224 + *
225 + * Copyright 2019 NXP
226 + *
227 + */
228 +
229 +&mdio_slot2 {
230 + /* 4 ports on AQR412 */
231 + slot2_qsgmii0: ethernet-phy@0 {
232 + reg = <0x0>;
233 + compatible = "ethernet-phy-ieee802.3-c45";
234 + };
235 + slot2_qsgmii1: ethernet-phy@1 {
236 + reg = <0x1>;
237 + compatible = "ethernet-phy-ieee802.3-c45";
238 + };
239 + slot2_qsgmii2: ethernet-phy@2 {
240 + reg = <0x2>;
241 + compatible = "ethernet-phy-ieee802.3-c45";
242 + };
243 + slot2_qsgmii3: ethernet-phy@3 {
244 + reg = <0x3>;
245 + compatible = "ethernet-phy-ieee802.3-c45";
246 + };
247 +};
248 +
249 +/* l2switch ports */
250 +&switch_port0 {
251 + phy-handle = <&slot2_qsgmii0>;
252 + phy-connection-type = "usxgmii";
253 +};
254 +
255 +&switch_port1 {
256 + phy-handle = <&slot2_qsgmii1>;
257 + phy-connection-type = "usxgmii";
258 +};
259 +
260 +&switch_port2 {
261 + phy-handle = <&slot2_qsgmii2>;
262 + phy-connection-type = "usxgmii";
263 +};
264 +
265 +&switch_port3 {
266 + phy-handle = <&slot2_qsgmii3>;
267 + phy-connection-type = "usxgmii";
268 +};
269 --- /dev/null
270 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi
271 @@ -0,0 +1,44 @@
272 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
273 +/*
274 + * Device Tree Include file for LS1028A QDS board, serdes x5xx
275 + *
276 + * Copyright 2019 NXP
277 + *
278 + */
279 +
280 +&mdio_slot2 {
281 + /* 4 ports on VSC8514 */
282 + slot2_qsgmii0: ethernet-phy@8 {
283 + reg = <0x8>;
284 + };
285 + slot2_qsgmii1: ethernet-phy@9 {
286 + reg = <0x9>;
287 + };
288 + slot2_qsgmii2: ethernet-phy@a {
289 + reg = <0xa>;
290 + };
291 + slot2_qsgmii3: ethernet-phy@b {
292 + reg = <0xb>;
293 + };
294 +};
295 +
296 +/* l2switch ports */
297 +&switch_port0 {
298 + phy-handle = <&slot2_qsgmii0>;
299 + phy-connection-type = "qsgmii";
300 +};
301 +
302 +&switch_port1 {
303 + phy-handle = <&slot2_qsgmii1>;
304 + phy-connection-type = "qsgmii";
305 +};
306 +
307 +&switch_port2 {
308 + phy-handle = <&slot2_qsgmii2>;
309 + phy-connection-type = "qsgmii";
310 +};
311 +
312 +&switch_port3 {
313 + phy-handle = <&slot2_qsgmii3>;
314 + phy-connection-type = "qsgmii";
315 +};
316 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
317 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
318 @@ -104,6 +104,30 @@
319 reg = <5>;
320 };
321 };
322 +
323 + mdio_slot1: mdio@4 {
324 + #address-cells = <1>;
325 + #size-cells = <0>;
326 + reg = <4>;
327 + };
328 +
329 + mdio_slot2: mdio@5 {
330 + #address-cells = <1>;
331 + #size-cells = <0>;
332 + reg = <5>;
333 + };
334 +
335 + mdio_slot3: mdio@6 {
336 + #address-cells = <1>;
337 + #size-cells = <0>;
338 + reg = <6>;
339 + };
340 +
341 + mdio_slot4: mdio@7 {
342 + #address-cells = <1>;
343 + #size-cells = <0>;
344 + reg = <7>;
345 + };
346 };
347 };
348
349 @@ -260,3 +284,6 @@
350 edp_num_lanes = <0x4>;
351 status = "okay";
352 };
353 +
354 +#include "fsl-ls1028a-qds-8xxx.dtsi"
355 +#include "fsl-ls1028a-qds-x5xx.dtsi"
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