8567d0802bcc6add84b08cbf0bab3705b8e09d57
[openwrt/staging/rmilecki.git] /
1 From e4cacac0cae3ce7399b70df3bce92eac03151624 Mon Sep 17 00:00:00 2001
2 From: Christian Marangi <ansuelsmth@gmail.com>
3 Date: Tue, 12 Apr 2022 16:48:39 +0200
4 Subject: [PATCH 3/4] clk: introduce (devm_)hw_register_mux_parent_data_table
5 API
6
7 Introduce (devm_)hw_register_mux_parent_data_table new API. We have
8 basic support for clk_register_mux using parent_data but we lack any API
9 to provide a custom parent_map. Add these 2 new API to correctly handle
10 these special configuration instead of using the generic
11 __(devm_)clk_hw_register_mux API.
12
13 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
14 ---
15 include/linux/clk-provider.h | 14 ++++++++++++++
16 1 file changed, 14 insertions(+)
17
18 --- a/include/linux/clk-provider.h
19 +++ b/include/linux/clk-provider.h
20 @@ -955,12 +955,26 @@ struct clk *clk_register_mux_table(struc
21 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
22 (parent_data), (flags), (reg), (shift), \
23 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
24 +#define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \
25 + num_parents, flags, reg, shift, \
26 + width, clk_mux_flags, table, \
27 + lock) \
28 + __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
29 + (parent_data), (flags), (reg), (shift), \
30 + BIT((width)) - 1, (clk_mux_flags), table, (lock))
31 #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
32 shift, width, clk_mux_flags, lock) \
33 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \
34 (parent_names), NULL, NULL, (flags), (reg), \
35 (shift), BIT((width)) - 1, (clk_mux_flags), \
36 NULL, (lock))
37 +#define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \
38 + num_parents, flags, reg, shift, \
39 + width, clk_mux_flags, table, \
40 + lock) \
41 + __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
42 + NULL, (parent_data), (flags), (reg), (shift), \
43 + BIT((width)) - 1, (clk_mux_flags), table, (lock))
44
45 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
46 unsigned int val);