git.openwrt.org Git - openwrt/staging/ynezz.git/blob

   1 From 7d11e6c1669b9134b11a48cdf47e5b7ab1b2396c Mon Sep 17 00:00:00 2001
   2 From: Bing Song <bing.song@nxp.com>
   3 Date: Fri, 5 Jan 2018 08:33:51 +0200
   4 Subject: [PATCH] MLK-17368-1 drm: add fourcc codes for Verisilicon tiled
   5  formats
   6
   7 These formats will be used by VPU and DCSS.
   8
   9 Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
  10 [ Aisheng : VENDOR_VSI changed to 0xf1 ]
  11 Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
  12 ---
  13  include/uapi/drm/drm_fourcc.h | 27 +++++++++++++++++++++++++++
  14  1 file changed, 27 insertions(+)
  15
  16 --- a/include/uapi/drm/drm_fourcc.h
  17 +++ b/include/uapi/drm/drm_fourcc.h
  18 @@ -310,6 +310,7 @@ extern "C" {
  19  #define DRM_FORMAT_MOD_VENDOR_ARM     0x08
  20  #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
  21  #define DRM_FORMAT_MOD_VENDOR_AMPHION 0xf0
  22 +#define DRM_FORMAT_MOD_VENDOR_VSI     0xf1
  23
  24  /* add more to the end as needed */
  25
  26 @@ -767,6 +768,32 @@ extern "C" {
  27   */
  28  #define DRM_FORMAT_MOD_AMPHION_TILED fourcc_mod_code(AMPHION, 1)
  29
  30 +/* Verisilicon framebuffer modifiers */
  31 +
  32 +/*
  33 + * Verisilicon 8x4 tiling layout
  34 + *
  35 + * This is G1 VPU tiled layout using tiles of 8x4 pixels in a row-major
  36 + * layout.
  37 + */
  38 +#define DRM_FORMAT_MOD_VSI_G1_TILED fourcc_mod_code(VSI, 1)
  39 +
  40 +/*
  41 + * Verisilicon 4x4 tiling layout
  42 + *
  43 + * This is G2 VPU tiled layout using tiles of 4x4 pixels in a row-major
  44 + * layout.
  45 + */
  46 +#define DRM_FORMAT_MOD_VSI_G2_TILED fourcc_mod_code(VSI, 2)
  47 +
  48 +/*
  49 + * Verisilicon 4x4 tiling with compression layout
  50 + *
  51 + * This is G2 VPU tiled layout using tiles of 4x4 pixels in a row-major
  52 + * layout with compression.
  53 + */
  54 +#define DRM_FORMAT_MOD_VSI_G2_TILED_COMPRESSED fourcc_mod_code(VSI, 3)
  55 +
  56  #if defined(__cplusplus)
  57  }
  58  #endif