git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From c45de75d7a9ab44a15dedc7a121d6371d6891301 Mon Sep 17 00:00:00 2001
   2 From: Trevor Woerner <twoerner@gmail.com>
   3 Date: Mon, 20 Nov 2023 11:22:32 -0500
   4 Subject: [PATCH] arm64: dts: rockchip: add gpio-line-names to rk3308-rock-pi-s
   5
   6 Add names to the pins of the general-purpose expansion header as given in the
   7 Radxa GPIO page[1] following the conventions in the kernel documentation[2] to
   8 make it easier for users to correlate the pins with functions when using
   9 utilities such as gpioinfo.
  10
  11 [1] https://wiki.radxa.com/RockpiS/hardware/gpio
  12 [2] Documentation/devicetree/bindings/gpio/gpio.txt
  13
  14 Signed-off-by: Trevor Woerner <twoerner@gmail.com>
  15 Link: https://lore.kernel.org/r/20231120162232.27653-1-twoerner@gmail.com
  16 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  17 ---
  18  .../boot/dts/rockchip/rk3308-rock-pi-s.dts    | 58 +++++++++++++++++++
  19  1 file changed, 58 insertions(+)
  20
  21 --- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
  22 +++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
  23 @@ -315,3 +315,61 @@
  24  &wdt {
  25         status = "okay";
  26  };
  27 +
  28 +&gpio0 {
  29 +       gpio-line-names =
  30 +       /* GPIO0_A0 - A7 */
  31 +       "", "", "", "", "", "", "", "",
  32 +       /* GPIO0_B0 - B7 */
  33 +       "", "", "", "header1-pin3 [GPIO0_B3]", "header1-pin5 [GPIO0_B4]",
  34 +       "", "", "header1-pin11 [GPIO0_B7]",
  35 +       /* GPIO0_C0 - C7 */
  36 +       "header1-pin13 [GPIO0_C0]", "header1-pin15 [GPIO0_C1]", "", "", "",
  37 +       "", "", "",
  38 +       /* GPIO0_D0 - D8 */
  39 +       "", "", "", "", "", "", "", "";
  40 +};
  41 +
  42 +&gpio1 {
  43 +       gpio-line-names =
  44 +       /* GPIO1_A0 - A7 */
  45 +       "", "", "", "", "", "", "", "",
  46 +       /* GPIO1_B0 - B7 */
  47 +       "", "", "", "", "", "", "", "",
  48 +       /* GPIO1_C0 - C7 */
  49 +       "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]",
  50 +       "header1-pin19 [GPIO1_C7]",
  51 +       /* GPIO1_D0 - D8 */
  52 +       "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", "", "", "",
  53 +       "", "", "";
  54 +};
  55 +
  56 +&gpio2 {
  57 +       gpio-line-names =
  58 +       /* GPIO2_A0 - A7 */
  59 +       "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", "", "",
  60 +       "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]",
  61 +       "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]",
  62 +       /* GPIO2_B0 - B7 */
  63 +       "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]",
  64 +       "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]",
  65 +       "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]",
  66 +       "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]",
  67 +       /* GPIO2_C0 - C7 */
  68 +       "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "",
  69 +       /* GPIO2_D0 - D8 */
  70 +       "", "", "", "", "", "", "", "";
  71 +};
  72 +
  73 +&gpio3 {
  74 +       gpio-line-names =
  75 +       /* GPIO3_A0 - A7 */
  76 +       "", "", "", "", "", "", "", "",
  77 +       /* GPIO3_B0 - B7 */
  78 +       "", "", "header2-pin42 [GPIO3_B2]", "header2-pin41 [GPIO3_B3]",
  79 +       "header2-pin40 [GPIO3_B4]", "header2-pin39 [GPIO3_B5]", "", "",
  80 +       /* GPIO3_C0 - C7 */
  81 +       "", "", "", "", "", "", "", "",
  82 +       /* GPIO3_D0 - D8 */
  83 +       "", "", "", "", "", "", "", "";
  84 +};