git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From e93fc4ed811c7dcc6b0c93716f760431fc645ba2 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Thu, 26 Dec 2019 15:48:09 +0100
   4 Subject: [PATCH] drm/vc4: crtc: Move the cob allocation outside of
   5  bind
   6
   7 The COB allocation depends on the HVS channel used for a given
   8 pixelvalve.
   9
  10 While the channel allocation was entirely static in vc4, vc5 changes
  11 that and at bind time, a pixelvalve can be assigned to multiple
  12 HVS channels.
  13
  14 Let's prepare that rework by allocating the COB when it's actually
  15 needed.
  16
  17 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  18 ---
  19  drivers/gpu/drm/vc4/vc4_crtc.c | 39 +++++++++++++++++-----------------
  20  drivers/gpu/drm/vc4/vc4_drv.h  |  2 --
  21  2 files changed, 20 insertions(+), 21 deletions(-)
  22
  23 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  24 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  25 @@ -65,6 +65,23 @@ static const struct debugfs_reg32 crtc_r
  26         VC4_REG32(PV_HACT_ACT),
  27  };
  28
  29 +static unsigned int
  30 +vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc, unsigned int channel)
  31 +{
  32 +       struct drm_device *drm = vc4_crtc->base.dev;
  33 +       struct vc4_dev *vc4 = to_vc4_dev(drm);
  34 +
  35 +       u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel));
  36 +       /* Top/base are supposed to be 4-pixel aligned, but the
  37 +        * Raspberry Pi firmware fills the low bits (which are
  38 +        * presumably ignored).
  39 +        */
  40 +       u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
  41 +       u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
  42 +
  43 +       return top - base + 4;
  44 +}
  45 +
  46  bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
  47                              bool in_vblank_irq, int *vpos, int *hpos,
  48                              ktime_t *stime, ktime_t *etime,
  49 @@ -73,6 +90,7 @@ bool vc4_crtc_get_scanoutpos(struct drm_
  50         struct vc4_dev *vc4 = to_vc4_dev(dev);
  51         struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
  52         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  53 +       unsigned int cob_size;
  54         u32 val;
  55         int fifo_lines;
  56         int vblank_lines;
  57 @@ -108,8 +126,9 @@ bool vc4_crtc_get_scanoutpos(struct drm_
  58                         *hpos += mode->crtc_htotal / 2;
  59         }
  60
  61 +       cob_size = vc4_crtc_get_cob_allocation(vc4_crtc, vc4_crtc->channel);
  62         /* This is the offset we need for translating hvs -> pv scanout pos. */
  63 -       fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
  64 +       fifo_lines = cob_size / mode->crtc_hdisplay;
  65
  66         if (fifo_lines > 0)
  67                 ret = true;
  68 @@ -1104,22 +1123,6 @@ static void vc4_set_crtc_possible_masks(
  69         }
  70  }
  71
  72 -static void
  73 -vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
  74 -{
  75 -       struct drm_device *drm = vc4_crtc->base.dev;
  76 -       struct vc4_dev *vc4 = to_vc4_dev(drm);
  77 -       u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
  78 -       /* Top/base are supposed to be 4-pixel aligned, but the
  79 -        * Raspberry Pi firmware fills the low bits (which are
  80 -        * presumably ignored).
  81 -        */
  82 -       u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
  83 -       u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
  84 -
  85 -       vc4_crtc->cob_size = top - base + 4;
  86 -}
  87 -
  88  static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
  89  {
  90         struct platform_device *pdev = to_platform_device(dev);
  91 @@ -1174,8 +1177,6 @@ static int vc4_crtc_bind(struct device *
  92          */
  93         drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
  94
  95 -       vc4_crtc_get_cob_allocation(vc4_crtc);
  96 -
  97         CRTC_WRITE(PV_INTEN, 0);
  98         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
  99         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
 100 --- a/drivers/gpu/drm/vc4/vc4_drv.h
 101 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
 102 @@ -477,8 +477,6 @@ struct vc4_crtc {
 103         u8 lut_r[256];
 104         u8 lut_g[256];
 105         u8 lut_b[256];
 106 -       /* Size in pixels of the COB memory allocated to this CRTC. */
 107 -       u32 cob_size;
 108
 109         struct drm_pending_vblank_event *event;
 110