git.openwrt.org Git - openwrt/staging/dedeckeh.git/blob

   1 From 7090c69d64c3871867e86adc5bf568d89608c965 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Tue, 29 Jun 2021 09:53:52 +0200
   4 Subject: [PATCH] drm/vc4: hdmi: Split the CEC disable / enable
   5  functions in two
   6
   7 In order to ease further additions to the CEC enable and disable, let's
   8 split the function into two functions, one to enable and the other to
   9 disable.
  10
  11 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  12 ---
  13  drivers/gpu/drm/vc4/vc4_hdmi.c | 75 ++++++++++++++++++++--------------
  14  1 file changed, 45 insertions(+), 30 deletions(-)
  15
  16 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
  17 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
  18 @@ -1755,7 +1755,7 @@ static irqreturn_t vc4_cec_irq_handler(i
  19         return ret;
  20  }
  21
  22 -static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
  23 +static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
  24  {
  25         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
  26         /* clock period in microseconds */
  27 @@ -1768,38 +1768,53 @@ static int vc4_hdmi_cec_adap_enable(stru
  28         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
  29                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
  30
  31 -       if (enable) {
  32 -               HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
  33 -                          VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
  34 -               HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
  35 -               HDMI_WRITE(HDMI_CEC_CNTRL_2,
  36 -                          ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
  37 -                          ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
  38 -                          ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
  39 -                          ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
  40 -                          ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
  41 -               HDMI_WRITE(HDMI_CEC_CNTRL_3,
  42 -                          ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
  43 -                          ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
  44 -                          ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
  45 -                          ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
  46 -               HDMI_WRITE(HDMI_CEC_CNTRL_4,
  47 -                          ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
  48 -                          ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
  49 -                          ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
  50 -                          ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
  51 -
  52 -               if (!vc4_hdmi->variant->external_irq_controller)
  53 -                       HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
  54 -       } else {
  55 -               if (!vc4_hdmi->variant->external_irq_controller)
  56 -                       HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
  57 -               HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
  58 -                          VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
  59 -       }
  60 +       HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
  61 +                  VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
  62 +       HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
  63 +       HDMI_WRITE(HDMI_CEC_CNTRL_2,
  64 +                  ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
  65 +                  ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
  66 +                  ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
  67 +                  ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
  68 +                  ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
  69 +       HDMI_WRITE(HDMI_CEC_CNTRL_3,
  70 +                  ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
  71 +                  ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
  72 +                  ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
  73 +                  ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
  74 +       HDMI_WRITE(HDMI_CEC_CNTRL_4,
  75 +                  ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
  76 +                  ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
  77 +                  ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
  78 +                  ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
  79 +
  80 +       if (!vc4_hdmi->variant->external_irq_controller)
  81 +               HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
  82 +
  83         return 0;
  84  }
  85
  86 +static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
  87 +{
  88 +       struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
  89 +
  90 +       if (!vc4_hdmi->variant->external_irq_controller)
  91 +               HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
  92 +
  93 +       HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
  94 +                  VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
  95 +
  96 +       return 0;
  97 +}
  98 +
  99 +static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
 100 +{
 101 +       if (enable)
 102 +               return vc4_hdmi_cec_enable(adap);
 103 +       else
 104 +               return vc4_hdmi_cec_disable(adap);
 105 +}
 106 +
 107  static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
 108  {
 109         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);