git.openwrt.org Git - openwrt/staging/wigyori.git/blob

   1 From 98feaf97bc64fc640a6c5b1394cd18fc7cd7dac8 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
   3 Date: Sun, 28 Mar 2021 14:34:49 +0200
   4 Subject: [PATCH] PCI: aardvark: Refactor unmasking summary MSI interrupt
   5 MIME-Version: 1.0
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   8
   9 Refactor the masking of ISR0/1 Sources and unmasking of summary MSI interrupt
  10 so that it corresponds to the comments:
  11 - first mask all ISR0/1
  12 - then unmask all MSIs
  13 - then unmask summary MSI interrupt
  14
  15 Signed-off-by: Pali Rohár <pali@kernel.org>
  16 Signed-off-by: Marek Behún <kabel@kernel.org>
  17 ---
  18  drivers/pci/controller/pci-aardvark.c | 10 ++++++----
  19  1 file changed, 6 insertions(+), 4 deletions(-)
  20
  21 diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
  22 index e641ad566488..5c887772fa97 100644
  23 --- a/drivers/pci/controller/pci-aardvark.c
  24 +++ b/drivers/pci/controller/pci-aardvark.c
  25 @@ -578,15 +578,17 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
  26         advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
  27
  28         /* Disable All ISR0/1 Sources */
  29 -       reg = PCIE_ISR0_ALL_MASK;
  30 -       reg &= ~PCIE_ISR0_MSI_INT_PENDING;
  31 -       advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
  32 -
  33 +       advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);
  34         advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
  35
  36         /* Unmask all MSIs */
  37         advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
  38
  39 +       /* Unmask summary MSI interrupt */
  40 +       reg = advk_readl(pcie, PCIE_ISR0_MASK_REG);
  41 +       reg &= ~PCIE_ISR0_MSI_INT_PENDING;
  42 +       advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
  43 +
  44         /* Enable summary interrupt for GIC SPI source */
  45         reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
  46         advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
  47 --
  48 2.34.1
  49