git.openwrt.org Git - openwrt/staging/ldir.git/blob

   1 From 0cf731f9ebb5bf6f252055bebf4463a5c0bd490b Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Tue, 23 Aug 2022 14:24:07 +0200
   4 Subject: [PATCH] net: ethernet: mtk_eth_soc: fix hw hash reporting for
   5  MTK_NETSYS_V2
   6
   7 Properly report hw rx hash for mt7986 chipset accroding to the new dma
   8 descriptor layout.
   9
  10 Fixes: 197c9e9b17b11 ("net: ethernet: mtk_eth_soc: introduce support for mt7986 chipset")
  11 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  12 Link: https://lore.kernel.org/r/091394ea4e705fbb35f828011d98d0ba33808f69.1661257293.git.lorenzo@kernel.org
  13 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  14 ---
  15  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 22 +++++++++++----------
  16  drivers/net/ethernet/mediatek/mtk_eth_soc.h |  5 +++++
  17  2 files changed, 17 insertions(+), 10 deletions(-)
  18
  19 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  20 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  21 @@ -1846,10 +1846,19 @@ static int mtk_poll_rx(struct napi_struc
  22                 skb->dev = netdev;
  23                 bytes += skb->len;
  24
  25 -               if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
  26 +               if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  27 +                       hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
  28 +                       if (hash != MTK_RXD5_FOE_ENTRY)
  29 +                               skb_set_hash(skb, jhash_1word(hash, 0),
  30 +                                            PKT_HASH_TYPE_L4);
  31                         rxdcsum = &trxd.rxd3;
  32 -               else
  33 +               } else {
  34 +                       hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY;
  35 +                       if (hash != MTK_RXD4_FOE_ENTRY)
  36 +                               skb_set_hash(skb, jhash_1word(hash, 0),
  37 +                                            PKT_HASH_TYPE_L4);
  38                         rxdcsum = &trxd.rxd4;
  39 +               }
  40
  41                 if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid)
  42                         skb->ip_summed = CHECKSUM_UNNECESSARY;
  43 @@ -1857,16 +1866,9 @@ static int mtk_poll_rx(struct napi_struc
  44                         skb_checksum_none_assert(skb);
  45                 skb->protocol = eth_type_trans(skb, netdev);
  46
  47 -               hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY;
  48 -               if (hash != MTK_RXD4_FOE_ENTRY) {
  49 -                       hash = jhash_1word(hash, 0);
  50 -                       skb_set_hash(skb, hash, PKT_HASH_TYPE_L4);
  51 -               }
  52 -
  53                 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4);
  54                 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
  55 -                       mtk_ppe_check_skb(eth->ppe, skb,
  56 -                                         trxd.rxd4 & MTK_RXD4_FOE_ENTRY);
  57 +                       mtk_ppe_check_skb(eth->ppe, skb, hash);
  58
  59                 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
  60                         if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  61 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  62 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  63 @@ -314,6 +314,11 @@
  64  #define RX_DMA_L4_VALID_PDMA   BIT(30)         /* when PDMA is used */
  65  #define RX_DMA_SPECIAL_TAG     BIT(22)
  66
  67 +/* PDMA descriptor rxd5 */
  68 +#define MTK_RXD5_FOE_ENTRY     GENMASK(14, 0)
  69 +#define MTK_RXD5_PPE_CPU_REASON        GENMASK(22, 18)
  70 +#define MTK_RXD5_SRC_PORT      GENMASK(29, 26)
  71 +
  72  #define RX_DMA_GET_SPORT(x)    (((x) >> 19) & 0xf)
  73  #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0x7)
  74