git.openwrt.org Git - openwrt/staging/nbd.git/blob

   1 From 4305650c92eef5921cc140c999eccbb6de1ab4b8 Mon Sep 17 00:00:00 2001
   2 From: Devi Priya <quic_devipriy@quicinc.com>
   3 Date: Fri, 25 Oct 2024 09:25:14 +0530
   4 Subject: [PATCH 1/7] clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL
   5  support for ipq9574
   6
   7 Add support for NSS Huayra alpha pll found on ipq9574 SoCs.
   8 Programming sequence is the same as that of Huayra type Alpha PLL,
   9 so we can re-use the same.
  10
  11 Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  12 Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
  13 Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
  14 ---
  15  drivers/clk/qcom/clk-alpha-pll.c | 11 +++++++++++
  16  drivers/clk/qcom/clk-alpha-pll.h |  1 +
  17  2 files changed, 12 insertions(+)
  18
  19 diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
  20 index f9105443d7db..c2e56e9403ff 100644
  21 --- a/drivers/clk/qcom/clk-alpha-pll.c
  22 +++ b/drivers/clk/qcom/clk-alpha-pll.c
  23 @@ -267,6 +267,17 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
  24                 [PLL_OFF_OPMODE] = 0x30,
  25                 [PLL_OFF_STATUS] = 0x3c,
  26         },
  27 +       [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] =  {
  28 +               [PLL_OFF_L_VAL] = 0x04,
  29 +               [PLL_OFF_ALPHA_VAL] = 0x08,
  30 +               [PLL_OFF_TEST_CTL] = 0x0c,
  31 +               [PLL_OFF_TEST_CTL_U] = 0x10,
  32 +               [PLL_OFF_USER_CTL] = 0x14,
  33 +               [PLL_OFF_CONFIG_CTL] = 0x18,
  34 +               [PLL_OFF_CONFIG_CTL_U] = 0x1c,
  35 +               [PLL_OFF_STATUS] = 0x20,
  36 +       },
  37 +
  38  };
  39  EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
  40
  41 diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
  42 index 55eca04b23a1..c6d1b8429f95 100644
  43 --- a/drivers/clk/qcom/clk-alpha-pll.h
  44 +++ b/drivers/clk/qcom/clk-alpha-pll.h
  45 @@ -32,6 +32,7 @@ enum {
  46         CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
  47         CLK_ALPHA_PLL_TYPE_STROMER,
  48         CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
  49 +       CLK_ALPHA_PLL_TYPE_NSS_HUAYRA,
  50         CLK_ALPHA_PLL_TYPE_MAX,
  51  };
  52
  53 --
  54 2.45.2
  55