git.openwrt.org Git - openwrt/staging/981213.git/blob

   1 From 478b09fa2c00cbc40d25bc061befdf11f04a27ad Mon Sep 17 00:00:00 2001
   2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   3 Date: Thu, 10 Feb 2022 10:48:58 +0100
   4 Subject: [PATCH 1/2] dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property
   5
   6 Make system controller a reset provider for all the peripherals in the
   7 MT7621 SoC adding '#reset-cells' property.
   8
   9 Acked-by: Rob Herring <robh@kernel.org>
  10 Acked-by: Stephen Boyd <sboyd@kernel.org>
  11 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  12 Link: https://lore.kernel.org/r/20220210094859.927868-2-sergio.paracuellos@gmail.com
  13 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  14 ---
  15  .../devicetree/bindings/clock/mediatek,mt7621-sysc.yaml      | 12 ++++++++++++
  16  1 file changed, 12 insertions(+)
  17
  18 --- a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
  19 +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
  20 @@ -22,6 +22,11 @@ description: |
  21
  22    The clocks are provided inside a system controller node.
  23
  24 +  This node is also a reset provider for all the peripherals.
  25 +
  26 +  Reset related bits are defined in:
  27 +  [2]: <include/dt-bindings/reset/mt7621-reset.h>.
  28 +
  29  properties:
  30    compatible:
  31      items:
  32 @@ -37,6 +42,12 @@ properties:
  33        clocks.
  34      const: 1
  35
  36 +  "#reset-cells":
  37 +    description:
  38 +      The first cell indicates the reset bit within the register, see
  39 +      [2] for available resets.
  40 +    const: 1
  41 +
  42    ralink,memctl:
  43      $ref: /schemas/types.yaml#/definitions/phandle
  44      description:
  45 @@ -61,6 +72,7 @@ examples:
  46        compatible = "mediatek,mt7621-sysc", "syscon";
  47        reg = <0x0 0x100>;
  48        #clock-cells = <1>;
  49 +      #reset-cells = <1>;
  50        ralink,memctl = <&memc>;
  51        clock-output-names = "xtal", "cpu", "bus",
  52                             "50m", "125m", "150m",