git.openwrt.org Git - openwrt/staging/wigyori.git/blob

   1 From 8b6f0330b5f9a7543356bfa9e76d580f03aa2c1e Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Mon, 15 Jun 2020 23:05:57 +0200
   4 Subject: PCI: qcom: Add missing ipq806x clocks in PCIe driver
   5
   6 Aux and Ref clk are missing in PCIe qcom driver. Add support for this
   7 optional clks for ipq8064/apq8064 SoC.
   8
   9 Link: https://lore.kernel.org/r/20200615210608.21469-2-ansuelsmth@gmail.com
  10 Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
  11 Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  12 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  13 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  14 Reviewed-by: Rob Herring <robh@kernel.org>
  15 Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  16 ---
  17  drivers/pci/controller/dwc/pcie-qcom.c | 38 +++++++++++++++++++++++++++++-----
  18  1 file changed, 33 insertions(+), 5 deletions(-)
  19
  20 --- a/drivers/pci/controller/dwc/pcie-qcom.c
  21 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
  22 @@ -85,6 +85,8 @@ struct qcom_pcie_resources_2_1_0 {
  23         struct clk *iface_clk;
  24         struct clk *core_clk;
  25         struct clk *phy_clk;
  26 +       struct clk *aux_clk;
  27 +       struct clk *ref_clk;
  28         struct reset_control *pci_reset;
  29         struct reset_control *axi_reset;
  30         struct reset_control *ahb_reset;
  31 @@ -235,6 +237,14 @@ static int qcom_pcie_get_resources_2_1_0
  32         if (IS_ERR(res->phy_clk))
  33                 return PTR_ERR(res->phy_clk);
  34
  35 +       res->aux_clk = devm_clk_get_optional(dev, "aux");
  36 +       if (IS_ERR(res->aux_clk))
  37 +               return PTR_ERR(res->aux_clk);
  38 +
  39 +       res->ref_clk = devm_clk_get_optional(dev, "ref");
  40 +       if (IS_ERR(res->ref_clk))
  41 +               return PTR_ERR(res->ref_clk);
  42 +
  43         res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
  44         if (IS_ERR(res->pci_reset))
  45                 return PTR_ERR(res->pci_reset);
  46 @@ -267,6 +277,8 @@ static void qcom_pcie_deinit_2_1_0(struc
  47         clk_disable_unprepare(res->iface_clk);
  48         clk_disable_unprepare(res->core_clk);
  49         clk_disable_unprepare(res->phy_clk);
  50 +       clk_disable_unprepare(res->aux_clk);
  51 +       clk_disable_unprepare(res->ref_clk);
  52         regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
  53  }
  54
  55 @@ -296,16 +308,28 @@ static int qcom_pcie_init_2_1_0(struct q
  56                 goto err_assert_ahb;
  57         }
  58
  59 +       ret = clk_prepare_enable(res->core_clk);
  60 +       if (ret) {
  61 +               dev_err(dev, "cannot prepare/enable core clock\n");
  62 +               goto err_clk_core;
  63 +       }
  64 +
  65         ret = clk_prepare_enable(res->phy_clk);
  66         if (ret) {
  67                 dev_err(dev, "cannot prepare/enable phy clock\n");
  68                 goto err_clk_phy;
  69         }
  70
  71 -       ret = clk_prepare_enable(res->core_clk);
  72 +       ret = clk_prepare_enable(res->aux_clk);
  73         if (ret) {
  74 -               dev_err(dev, "cannot prepare/enable core clock\n");
  75 -               goto err_clk_core;
  76 +               dev_err(dev, "cannot prepare/enable aux clock\n");
  77 +               goto err_clk_aux;
  78 +       }
  79 +
  80 +       ret = clk_prepare_enable(res->ref_clk);
  81 +       if (ret) {
  82 +               dev_err(dev, "cannot prepare/enable ref clock\n");
  83 +               goto err_clk_ref;
  84         }
  85
  86         ret = reset_control_deassert(res->ahb_reset);
  87 @@ -361,10 +385,14 @@ static int qcom_pcie_init_2_1_0(struct q
  88         return 0;
  89
  90  err_deassert_ahb:
  91 -       clk_disable_unprepare(res->core_clk);
  92 -err_clk_core:
  93 +       clk_disable_unprepare(res->ref_clk);
  94 +err_clk_ref:
  95 +       clk_disable_unprepare(res->aux_clk);
  96 +err_clk_aux:
  97         clk_disable_unprepare(res->phy_clk);
  98  err_clk_phy:
  99 +       clk_disable_unprepare(res->core_clk);
 100 +err_clk_core:
 101         clk_disable_unprepare(res->iface_clk);
 102  err_assert_ahb:
 103         regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);