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1 From d96ec0527b0f5618b3a0757b47606705555ee996 Mon Sep 17 00:00:00 2001
2 From: Lei Wei <quic_leiwei@quicinc.com>
3 Date: Mon, 15 Apr 2024 11:06:02 +0800
4 Subject: [PATCH 15/50] net:pcs: Add 10G_QXGMII interface mode support to IPQ
5 UNIPHY PCS driver
6
7 10G_QXGMII is used when PCS connectes with QCA8084 four ports
8 2.5G PHYs.
9
10 Change-Id: If3dc92a07ac3e51f7c9473fb05fa0668617916fb
11 Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
12 ---
13 drivers/net/pcs/pcs-qcom-ipq-uniphy.c | 174 +++++++++++++++++++++-----
14 1 file changed, 142 insertions(+), 32 deletions(-)
15
16 diff --git a/drivers/net/pcs/pcs-qcom-ipq-uniphy.c b/drivers/net/pcs/pcs-qcom-ipq-uniphy.c
17 index 820d197744e8..a98180c91632 100644
18 --- a/drivers/net/pcs/pcs-qcom-ipq-uniphy.c
19 +++ b/drivers/net/pcs/pcs-qcom-ipq-uniphy.c
20 @@ -50,6 +50,9 @@
21 #define PCS_CHANNEL_STS_PAUSE_TX_EN BIT(1)
22 #define PCS_CHANNEL_STS_PAUSE_RX_EN BIT(0)
23
24 +#define PCS_QP_USXG_OPTION 0x584
25 +#define PCS_QP_USXG_GMII_SRC_XPCS BIT(0)
26 +
27 #define PCS_PLL_RESET 0x780
28 #define PCS_ANA_SW_RESET BIT(6)
29
30 @@ -65,10 +68,22 @@
31 #define XPCS_10GBASER_LINK_STS BIT(12)
32
33 #define XPCS_DIG_CTRL 0x38000
34 +#define XPCS_SOFT_RESET BIT(15)
35 #define XPCS_USXG_ADPT_RESET BIT(10)
36 #define XPCS_USXG_EN BIT(9)
37
38 +#define XPCS_KR_CTRL 0x38007
39 +#define XPCS_USXG_MODE_MASK GENMASK(12, 10)
40 +#define XPCS_10G_QXGMII_MODE FIELD_PREP(XPCS_USXG_MODE_MASK, 0x5)
41 +
42 +#define XPCS_DIG_STS 0x3800a
43 +#define XPCS_DIG_STS_AM_COUNT GENMASK(14, 0)
44 +
45 +#define XPCS_CHANNEL_DIG_CTRL(x) (0x1a8000 + 0x10000 * ((x) - 1))
46 +#define XPCS_CHANNEL_USXG_ADPT_RESET BIT(5)
47 +
48 #define XPCS_MII_CTRL 0x1f0000
49 +#define XPCS_CHANNEL_MII_CTRL(x) (0x1a0000 + 0x10000 * ((x) - 1))
50 #define XPCS_MII_AN_EN BIT(12)
51 #define XPCS_DUPLEX_FULL BIT(8)
52 #define XPCS_SPEED_MASK (BIT(13) | BIT(6) | BIT(5))
53 @@ -80,9 +95,11 @@
54 #define XPCS_SPEED_10 0
55
56 #define XPCS_MII_AN_CTRL 0x1f8001
57 +#define XPCS_CHANNEL_MII_AN_CTRL(x) (0x1a8001 + 0x10000 * ((x) - 1))
58 #define XPCS_MII_AN_8BIT BIT(8)
59
60 #define XPCS_MII_AN_INTR_STS 0x1f8002
61 +#define XPCS_CHANNEL_MII_AN_INTR_STS(x) (0x1a8002 + 0x10000 * ((x) - 1))
62 #define XPCS_USXG_AN_LINK_STS BIT(14)
63 #define XPCS_USXG_AN_DUPLEX_FULL BIT(13)
64 #define XPCS_USXG_AN_SPEED_MASK GENMASK(12, 10)
65 @@ -93,6 +110,10 @@
66 #define XPCS_USXG_AN_SPEED_5000 5
67 #define XPCS_USXG_AN_SPEED_10000 3
68
69 +#define XPCS_XAUI_MODE_CTRL 0x1f8004
70 +#define XPCS_CHANNEL_XAUI_MODE_CTRL(x) (0x1a8004 + 0x10000 * ((x) - 1))
71 +#define XPCS_TX_IPG_CHECK_DIS BIT(0)
72 +
73 /* UNIPHY PCS RAW clock ID */
74 enum {
75 PCS_RAW_RX_CLK = 0,
76 @@ -153,6 +174,7 @@ struct ipq_uniphy_pcs {
77 struct device *dev;
78 phy_interface_t interface;
79 struct mutex shared_lock; /* Lock to protect shared config */
80 + spinlock_t reg_lock; /* Lock for register access */
81 struct clk *clk[PCS_CLK_MAX];
82 struct reset_control *reset[PCS_RESET_MAX];
83 struct ipq_unipcs_raw_clk raw_clk[PCS_RAW_CLK_MAX];
84 @@ -215,39 +237,55 @@ static const struct clk_ops ipq_unipcs_raw_clk_ops = {
85
86 static u32 ipq_unipcs_reg_read32(struct ipq_uniphy_pcs *qunipcs, u32 reg)
87 {
88 + u32 val;
89 +
90 /* PCS use direct AHB access while XPCS use indirect AHB access */
91 if (reg >= XPCS_INDIRECT_ADDR) {
92 + /* For XPCS, althrough the register is different for different
93 + * channels, but they use the same indirect AHB address to
94 + * access, so add protects here.
95 + */
96 + spin_lock(&qunipcs->reg_lock);
97 +
98 writel(FIELD_GET(XPCS_INDIRECT_ADDR_H, reg),
99 qunipcs->base + XPCS_INDIRECT_AHB_ADDR);
100 - return readl(qunipcs->base + XPCS_INDIRECT_DATA_ADDR(reg));
101 + val = readl(qunipcs->base + XPCS_INDIRECT_DATA_ADDR(reg));
102 +
103 + spin_unlock(&qunipcs->reg_lock);
104 + return val;
105 } else {
106 return readl(qunipcs->base + reg);
107 }
108 }
109
110 -static void ipq_unipcs_reg_write32(struct ipq_uniphy_pcs *qunipcs,
111 - u32 reg, u32 val)
112 +static void ipq_unipcs_reg_modify32(struct ipq_uniphy_pcs *qunipcs,
113 + u32 reg, u32 mask, u32 set)
114 {
115 + u32 val;
116 +
117 if (reg >= XPCS_INDIRECT_ADDR) {
118 + spin_lock(&qunipcs->reg_lock);
119 +
120 + /* XPCS read */
121 writel(FIELD_GET(XPCS_INDIRECT_ADDR_H, reg),
122 qunipcs->base + XPCS_INDIRECT_AHB_ADDR);
123 + val = readl(qunipcs->base + XPCS_INDIRECT_DATA_ADDR(reg));
124 +
125 + val &= ~mask;
126 + val |= set;
127 +
128 + /* XPCS write */
129 writel(val, qunipcs->base + XPCS_INDIRECT_DATA_ADDR(reg));
130 +
131 + spin_unlock(&qunipcs->reg_lock);
132 } else {
133 + val = readl(qunipcs->base + reg);
134 + val &= ~mask;
135 + val |= set;
136 writel(val, qunipcs->base + reg);
137 }
138 }
139
140 -static void ipq_unipcs_reg_modify32(struct ipq_uniphy_pcs *qunipcs,
141 - u32 reg, u32 mask, u32 set)
142 -{
143 - u32 val;
144 -
145 - val = ipq_unipcs_reg_read32(qunipcs, reg);
146 - val &= ~mask;
147 - val |= set;
148 - ipq_unipcs_reg_write32(qunipcs, reg, val);
149 -}
150 -
151 static void ipq_unipcs_get_state_sgmii(struct ipq_uniphy_pcs *qunipcs,
152 int channel,
153 struct phylink_link_state *state)
154 @@ -305,11 +343,15 @@ static void ipq_unipcs_get_state_2500basex(struct ipq_uniphy_pcs *qunipcs,
155 }
156
157 static void ipq_unipcs_get_state_usxgmii(struct ipq_uniphy_pcs *qunipcs,
158 + int channel,
159 struct phylink_link_state *state)
160 {
161 - u32 val;
162 + u32 val, reg;
163 +
164 + reg = (channel == 0) ? XPCS_MII_AN_INTR_STS :
165 + XPCS_CHANNEL_MII_AN_INTR_STS(channel);
166
167 - val = ipq_unipcs_reg_read32(qunipcs, XPCS_MII_AN_INTR_STS);
168 + val = ipq_unipcs_reg_read32(qunipcs, reg);
169
170 state->link = !!(val & XPCS_USXG_AN_LINK_STS);
171
172 @@ -415,6 +457,15 @@ static int ipq_unipcs_config_mode(struct ipq_uniphy_pcs *qunipcs,
173 PCS_MODE_SEL_MASK,
174 PCS_MODE_XPCS);
175 break;
176 + case PHY_INTERFACE_MODE_10G_QXGMII:
177 + rate = 312500000;
178 + ipq_unipcs_reg_modify32(qunipcs, PCS_MODE_CTRL,
179 + PCS_MODE_SEL_MASK,
180 + PCS_MODE_XPCS);
181 + ipq_unipcs_reg_modify32(qunipcs, PCS_QP_USXG_OPTION,
182 + PCS_QP_USXG_GMII_SRC_XPCS,
183 + PCS_QP_USXG_GMII_SRC_XPCS);
184 + break;
185 default:
186 dev_err(qunipcs->dev,
187 "interface %s not supported\n", phy_modes(interface));
188 @@ -502,35 +553,82 @@ static int ipq_unipcs_config_2500basex(struct ipq_uniphy_pcs *qunipcs,
189 }
190
191 static int ipq_unipcs_config_usxgmii(struct ipq_uniphy_pcs *qunipcs,
192 + int channel,
193 unsigned int neg_mode,
194 phy_interface_t interface)
195 {
196 int ret;
197 + u32 reg;
198 +
199 + /* Only in-band autoneg mode is supported currently */
200 + if (neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED)
201 + return -EOPNOTSUPP;
202 +
203 + if (interface == PHY_INTERFACE_MODE_10G_QXGMII)
204 + mutex_lock(&qunipcs->shared_lock);
205
206 if (qunipcs->interface != interface) {
207 ret = ipq_unipcs_config_mode(qunipcs, interface);
208 if (ret)
209 - return ret;
210 + goto err;
211
212 - /* Deassert XPCS and configure XPCS USXGMII */
213 + /* Deassert XPCS and configure XPCS USXGMII or 10G_QXGMII */
214 reset_control_deassert(qunipcs->reset[XPCS_RESET]);
215
216 ipq_unipcs_reg_modify32(qunipcs, XPCS_DIG_CTRL,
217 XPCS_USXG_EN, XPCS_USXG_EN);
218
219 - if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
220 - ipq_unipcs_reg_modify32(qunipcs, XPCS_MII_AN_CTRL,
221 - XPCS_MII_AN_8BIT,
222 - XPCS_MII_AN_8BIT);
223 + if (interface == PHY_INTERFACE_MODE_10G_QXGMII) {
224 + ipq_unipcs_reg_modify32(qunipcs, XPCS_KR_CTRL,
225 + XPCS_USXG_MODE_MASK,
226 + XPCS_10G_QXGMII_MODE);
227 +
228 + /* Set Alignment Marker Interval */
229 + ipq_unipcs_reg_modify32(qunipcs, XPCS_DIG_STS,
230 + XPCS_DIG_STS_AM_COUNT,
231 + 0x6018);
232
233 - ipq_unipcs_reg_modify32(qunipcs, XPCS_MII_CTRL,
234 - XPCS_MII_AN_EN, XPCS_MII_AN_EN);
235 + ipq_unipcs_reg_modify32(qunipcs, XPCS_DIG_CTRL,
236 + XPCS_SOFT_RESET,
237 + XPCS_SOFT_RESET);
238 }
239
240 qunipcs->interface = interface;
241 }
242
243 + if (interface == PHY_INTERFACE_MODE_10G_QXGMII)
244 + mutex_unlock(&qunipcs->shared_lock);
245 +
246 + /* Disable Tx IPG check for 10G_QXGMII */
247 + if (interface == PHY_INTERFACE_MODE_10G_QXGMII) {
248 + reg = (channel == 0) ? XPCS_XAUI_MODE_CTRL :
249 + XPCS_CHANNEL_XAUI_MODE_CTRL(channel);
250 +
251 + ipq_unipcs_reg_modify32(qunipcs, reg,
252 + XPCS_TX_IPG_CHECK_DIS,
253 + XPCS_TX_IPG_CHECK_DIS);
254 + }
255 +
256 + /* Enable autoneg */
257 + reg = (channel == 0) ? XPCS_MII_AN_CTRL :
258 + XPCS_CHANNEL_MII_AN_CTRL(channel);
259 +
260 + ipq_unipcs_reg_modify32(qunipcs, reg,
261 + XPCS_MII_AN_8BIT, XPCS_MII_AN_8BIT);
262 +
263 + reg = (channel == 0) ? XPCS_MII_CTRL :
264 + XPCS_CHANNEL_MII_CTRL(channel);
265 +
266 + ipq_unipcs_reg_modify32(qunipcs, reg,
267 + XPCS_MII_AN_EN, XPCS_MII_AN_EN);
268 +
269 return 0;
270 +
271 +err:
272 + if (interface == PHY_INTERFACE_MODE_10G_QXGMII)
273 + mutex_unlock(&qunipcs->shared_lock);
274 +
275 + return ret;
276 }
277
278 static int ipq_unipcs_config_10gbaser(struct ipq_uniphy_pcs *qunipcs,
279 @@ -638,6 +736,7 @@ ipq_unipcs_link_up_clock_rate_set(struct ipq_uniphy_pcs_ch *qunipcs_ch,
280 break;
281 case PHY_INTERFACE_MODE_USXGMII:
282 case PHY_INTERFACE_MODE_10GBASER:
283 + case PHY_INTERFACE_MODE_10G_QXGMII:
284 rate = ipq_unipcs_clock_rate_get_xgmii(speed);
285 break;
286 default:
287 @@ -713,9 +812,10 @@ static void ipq_unipcs_link_up_config_2500basex(struct ipq_uniphy_pcs *qunipcs,
288 }
289
290 static void ipq_unipcs_link_up_config_usxgmii(struct ipq_uniphy_pcs *qunipcs,
291 + int channel,
292 int speed)
293 {
294 - u32 val;
295 + u32 val, reg;
296
297 switch (speed) {
298 case SPEED_10000:
299 @@ -744,14 +844,20 @@ static void ipq_unipcs_link_up_config_usxgmii(struct ipq_uniphy_pcs *qunipcs,
300 val |= XPCS_DUPLEX_FULL;
301
302 /* Config XPCS speed */
303 - ipq_unipcs_reg_modify32(qunipcs, XPCS_MII_CTRL,
304 + reg = (channel == 0) ? XPCS_MII_CTRL : XPCS_CHANNEL_MII_CTRL(channel);
305 + ipq_unipcs_reg_modify32(qunipcs, reg,
306 XPCS_SPEED_MASK | XPCS_DUPLEX_FULL,
307 val);
308
309 /* XPCS adapter reset */
310 - ipq_unipcs_reg_modify32(qunipcs, XPCS_DIG_CTRL,
311 - XPCS_USXG_ADPT_RESET,
312 - XPCS_USXG_ADPT_RESET);
313 + if (channel == 0)
314 + ipq_unipcs_reg_modify32(qunipcs, XPCS_DIG_CTRL,
315 + XPCS_USXG_ADPT_RESET,
316 + XPCS_USXG_ADPT_RESET);
317 + else
318 + ipq_unipcs_reg_modify32(qunipcs, XPCS_CHANNEL_DIG_CTRL(channel),
319 + XPCS_CHANNEL_USXG_ADPT_RESET,
320 + XPCS_CHANNEL_USXG_ADPT_RESET);
321 }
322
323 static int ipq_unipcs_validate(struct phylink_pcs *pcs,
324 @@ -786,7 +892,8 @@ static void ipq_unipcs_get_state(struct phylink_pcs *pcs,
325 ipq_unipcs_get_state_2500basex(qunipcs, channel, state);
326 break;
327 case PHY_INTERFACE_MODE_USXGMII:
328 - ipq_unipcs_get_state_usxgmii(qunipcs, state);
329 + case PHY_INTERFACE_MODE_10G_QXGMII:
330 + ipq_unipcs_get_state_usxgmii(qunipcs, channel, state);
331 break;
332 case PHY_INTERFACE_MODE_10GBASER:
333 ipq_unipcs_get_state_10gbaser(qunipcs, state);
334 @@ -823,7 +930,8 @@ static int ipq_unipcs_config(struct phylink_pcs *pcs,
335 case PHY_INTERFACE_MODE_2500BASEX:
336 return ipq_unipcs_config_2500basex(qunipcs, interface);
337 case PHY_INTERFACE_MODE_USXGMII:
338 - return ipq_unipcs_config_usxgmii(qunipcs,
339 + case PHY_INTERFACE_MODE_10G_QXGMII:
340 + return ipq_unipcs_config_usxgmii(qunipcs, channel,
341 neg_mode, interface);
342 case PHY_INTERFACE_MODE_10GBASER:
343 return ipq_unipcs_config_10gbaser(qunipcs, interface);
344 @@ -865,7 +973,8 @@ static void ipq_unipcs_link_up(struct phylink_pcs *pcs,
345 channel, speed);
346 break;
347 case PHY_INTERFACE_MODE_USXGMII:
348 - ipq_unipcs_link_up_config_usxgmii(qunipcs, speed);
349 + case PHY_INTERFACE_MODE_10G_QXGMII:
350 + ipq_unipcs_link_up_config_usxgmii(qunipcs, channel, speed);
351 break;
352 case PHY_INTERFACE_MODE_10GBASER:
353 break;
354 @@ -1082,6 +1191,7 @@ static int ipq_uniphy_probe(struct platform_device *pdev)
355 return ret;
356
357 mutex_init(&priv->shared_lock);
358 + spin_lock_init(&priv->reg_lock);
359
360 platform_set_drvdata(pdev, priv);
361
362 --
363 2.45.2
364
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