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1 From 6fb760972c49490b03f3db2ad64cf30bdd28c54a Mon Sep 17 00:00:00 2001
2 From: Christian Marangi <ansuelsmth@gmail.com>
3 Date: Mon, 29 Jan 2024 15:15:20 +0100
4 Subject: [PATCH 2/5] net: phy: qcom: create and move functions to shared
5 library
6
7 Create and move functions to shared library in preparation for qca83xx
8 PHY Family to be detached from at803x driver.
9
10 Only the shared defines are moved to the shared qcom.h header.
11
12 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
13 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
14 Link: https://lore.kernel.org/r/20240129141600.2592-3-ansuelsmth@gmail.com
15 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
16 ---
17 drivers/net/phy/qcom/Kconfig | 4 ++
18 drivers/net/phy/qcom/Makefile | 1 +
19 drivers/net/phy/qcom/at803x.c | 69 +----------------------------
20 drivers/net/phy/qcom/qcom-phy-lib.c | 53 ++++++++++++++++++++++
21 drivers/net/phy/qcom/qcom.h | 34 ++++++++++++++
22 5 files changed, 94 insertions(+), 67 deletions(-)
23 create mode 100644 drivers/net/phy/qcom/qcom-phy-lib.c
24 create mode 100644 drivers/net/phy/qcom/qcom.h
25
26 --- a/drivers/net/phy/qcom/Kconfig
27 +++ b/drivers/net/phy/qcom/Kconfig
28 @@ -1,6 +1,10 @@
29 # SPDX-License-Identifier: GPL-2.0-only
30 +config QCOM_NET_PHYLIB
31 + tristate
32 +
33 config AT803X_PHY
34 tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs"
35 + select QCOM_NET_PHYLIB
36 depends on REGULATOR
37 help
38 Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
39 --- a/drivers/net/phy/qcom/Makefile
40 +++ b/drivers/net/phy/qcom/Makefile
41 @@ -1,2 +1,3 @@
42 # SPDX-License-Identifier: GPL-2.0
43 +obj-$(CONFIG_QCOM_NET_PHYLIB) += qcom-phy-lib.o
44 obj-$(CONFIG_AT803X_PHY) += at803x.o
45 --- a/drivers/net/phy/qcom/at803x.c
46 +++ b/drivers/net/phy/qcom/at803x.c
47 @@ -22,6 +22,8 @@
48 #include <linux/sfp.h>
49 #include <dt-bindings/net/qca-ar803x.h>
50
51 +#include "qcom.h"
52 +
53 #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10
54 #define AT803X_SFC_ASSERT_CRS BIT(11)
55 #define AT803X_SFC_FORCE_LINK BIT(10)
56 @@ -84,9 +86,6 @@
57 #define AT803X_REG_CHIP_CONFIG 0x1f
58 #define AT803X_BT_BX_REG_SEL 0x8000
59
60 -#define AT803X_DEBUG_ADDR 0x1D
61 -#define AT803X_DEBUG_DATA 0x1E
62 -
63 #define AT803X_MODE_CFG_MASK 0x0F
64 #define AT803X_MODE_CFG_BASET_RGMII 0x00
65 #define AT803X_MODE_CFG_BASET_SGMII 0x01
66 @@ -103,19 +102,6 @@
67 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
68 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200
69
70 -#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00
71 -#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2)
72 -#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2)
73 -#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
74 -
75 -#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05
76 -#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
77 -
78 -#define AT803X_DEBUG_REG_HIB_CTRL 0x0b
79 -#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10)
80 -#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13)
81 -#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15)
82 -
83 #define AT803X_DEBUG_REG_3C 0x3C
84
85 #define AT803X_DEBUG_REG_GREEN 0x3D
86 @@ -393,18 +379,6 @@ MODULE_DESCRIPTION("Qualcomm Atheros AR8
87 MODULE_AUTHOR("Matus Ujhelyi");
88 MODULE_LICENSE("GPL");
89
90 -enum stat_access_type {
91 - PHY,
92 - MMD
93 -};
94 -
95 -struct at803x_hw_stat {
96 - const char *string;
97 - u8 reg;
98 - u32 mask;
99 - enum stat_access_type access_type;
100 -};
101 -
102 static struct at803x_hw_stat qca83xx_hw_stats[] = {
103 { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
104 { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
105 @@ -439,45 +413,6 @@ struct at803x_context {
106 u16 led_control;
107 };
108
109 -static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
110 -{
111 - int ret;
112 -
113 - ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
114 - if (ret < 0)
115 - return ret;
116 -
117 - return phy_write(phydev, AT803X_DEBUG_DATA, data);
118 -}
119 -
120 -static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
121 -{
122 - int ret;
123 -
124 - ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
125 - if (ret < 0)
126 - return ret;
127 -
128 - return phy_read(phydev, AT803X_DEBUG_DATA);
129 -}
130 -
131 -static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
132 - u16 clear, u16 set)
133 -{
134 - u16 val;
135 - int ret;
136 -
137 - ret = at803x_debug_reg_read(phydev, reg);
138 - if (ret < 0)
139 - return ret;
140 -
141 - val = ret & 0xffff;
142 - val &= ~clear;
143 - val |= set;
144 -
145 - return phy_write(phydev, AT803X_DEBUG_DATA, val);
146 -}
147 -
148 static int at803x_write_page(struct phy_device *phydev, int page)
149 {
150 int mask;
151 --- /dev/null
152 +++ b/drivers/net/phy/qcom/qcom-phy-lib.c
153 @@ -0,0 +1,53 @@
154 +// SPDX-License-Identifier: GPL-2.0
155 +
156 +#include <linux/phy.h>
157 +#include <linux/module.h>
158 +
159 +#include "qcom.h"
160 +
161 +MODULE_DESCRIPTION("Qualcomm PHY driver Common Functions");
162 +MODULE_AUTHOR("Matus Ujhelyi");
163 +MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
164 +MODULE_LICENSE("GPL");
165 +
166 +int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
167 +{
168 + int ret;
169 +
170 + ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
171 + if (ret < 0)
172 + return ret;
173 +
174 + return phy_read(phydev, AT803X_DEBUG_DATA);
175 +}
176 +EXPORT_SYMBOL_GPL(at803x_debug_reg_read);
177 +
178 +int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
179 + u16 clear, u16 set)
180 +{
181 + u16 val;
182 + int ret;
183 +
184 + ret = at803x_debug_reg_read(phydev, reg);
185 + if (ret < 0)
186 + return ret;
187 +
188 + val = ret & 0xffff;
189 + val &= ~clear;
190 + val |= set;
191 +
192 + return phy_write(phydev, AT803X_DEBUG_DATA, val);
193 +}
194 +EXPORT_SYMBOL_GPL(at803x_debug_reg_mask);
195 +
196 +int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
197 +{
198 + int ret;
199 +
200 + ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
201 + if (ret < 0)
202 + return ret;
203 +
204 + return phy_write(phydev, AT803X_DEBUG_DATA, data);
205 +}
206 +EXPORT_SYMBOL_GPL(at803x_debug_reg_write);
207 --- /dev/null
208 +++ b/drivers/net/phy/qcom/qcom.h
209 @@ -0,0 +1,34 @@
210 +/* SPDX-License-Identifier: GPL-2.0 */
211 +
212 +#define AT803X_DEBUG_ADDR 0x1D
213 +#define AT803X_DEBUG_DATA 0x1E
214 +
215 +#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00
216 +#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2)
217 +#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2)
218 +#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
219 +
220 +#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05
221 +#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
222 +
223 +#define AT803X_DEBUG_REG_HIB_CTRL 0x0b
224 +#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10)
225 +#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13)
226 +#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15)
227 +
228 +enum stat_access_type {
229 + PHY,
230 + MMD
231 +};
232 +
233 +struct at803x_hw_stat {
234 + const char *string;
235 + u8 reg;
236 + u32 mask;
237 + enum stat_access_type access_type;
238 +};
239 +
240 +int at803x_debug_reg_read(struct phy_device *phydev, u16 reg);
241 +int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
242 + u16 clear, u16 set);
243 +int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data);
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