projects / openwrt / staging / neocturne.git / blob
? search:


7cb4e5661d020ff6dbc4bc0ea236ff13e3817840
[openwrt/staging/neocturne.git] /
1 From 1bb54596ae2a9a36f4aa9f8f2ba941320f463811 Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime@cerno.tech>
3 Date: Fri, 17 Feb 2023 15:34:30 +0100
4 Subject: [PATCH] drm/vc4: hdmi: Add support for BCM2712 HDMI controllers
5
6 The HDMI controllers found in the BCM2712 are largely the ones found in
7 the BCM2711 with a different PHY.
8
9 There's some difference with how timings are split between registers,
10 and HDMI1 is now able to run at 4k/60Hz.
11
12 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
13 ---
14 drivers/gpu/drm/vc4/vc4_hdmi.c | 82 +++-
15 drivers/gpu/drm/vc4/vc4_hdmi.h | 4 +
16 drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 640 ++++++++++++++++++++++++++++
17 drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 217 ++++++++++
18 4 files changed, 937 insertions(+), 6 deletions(-)
19
20 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
21 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
22 @@ -1127,6 +1127,7 @@ static void vc4_hdmi_encoder_post_crtc_d
23 {
24 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
25 struct drm_device *drm = vc4_hdmi->connector.dev;
26 + struct vc4_dev *vc4 = to_vc4_dev(drm);
27 unsigned long flags;
28 int idx;
29
30 @@ -1143,14 +1144,25 @@ static void vc4_hdmi_encoder_post_crtc_d
31
32 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
33
34 + if (vc4->gen >= VC4_GEN_6)
35 + HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
36 + VC4_HD_VID_CTL_BLANKPIX);
37 +
38 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
39
40 mdelay(1);
41
42 - spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
43 - HDMI_WRITE(HDMI_VID_CTL,
44 - HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
45 - spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
46 + /*
47 + * TODO: This should work on BCM2712, but doesn't for some
48 + * reason and result in a system lockup.
49 + */
50 + if (vc4->gen < VC4_GEN_6) {
51 + spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
52 + HDMI_WRITE(HDMI_VID_CTL,
53 + HDMI_READ(HDMI_VID_CTL) &
54 + ~VC4_HD_VID_CTL_ENABLE);
55 + spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
56 + }
57
58 vc4_hdmi_disable_scrambling(encoder);
59
60 @@ -1757,7 +1769,6 @@ static void vc4_hdmi_encoder_pre_crtc_co
61 goto err_put_runtime_pm;
62 }
63
64 -
65 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
66
67 if (tmds_char_rate > 297000000)
68 @@ -1862,6 +1873,7 @@ static void vc4_hdmi_encoder_post_crtc_e
69 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
70
71 HDMI_WRITE(HDMI_VID_CTL,
72 + HDMI_READ(HDMI_VID_CTL) |
73 VC4_HD_VID_CTL_ENABLE |
74 VC4_HD_VID_CTL_CLRRGB |
75 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
76 @@ -3796,7 +3808,9 @@ static int vc4_hdmi_bind(struct device *
77 return ret;
78
79 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
80 - of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
81 + of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1") ||
82 + of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi0") ||
83 + of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi1")) &&
84 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
85 clk_prepare_enable(vc4_hdmi->pixel_clock);
86 clk_prepare_enable(vc4_hdmi->hsm_clock);
87 @@ -3931,10 +3945,66 @@ static const struct vc4_hdmi_variant bcm
88 .hp_detect = vc5_hdmi_hp_detect,
89 };
90
91 +static const struct vc4_hdmi_variant bcm2712_hdmi0_variant = {
92 + .encoder_type = VC4_ENCODER_TYPE_HDMI0,
93 + .debugfs_name = "hdmi0_regs",
94 + .card_name = "vc4-hdmi-0",
95 + .max_pixel_clock = 600000000,
96 + .registers = vc6_hdmi_hdmi0_fields,
97 + .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi0_fields),
98 + .phy_lane_mapping = {
99 + PHY_LANE_0,
100 + PHY_LANE_1,
101 + PHY_LANE_2,
102 + PHY_LANE_CK,
103 + },
104 + .unsupported_odd_h_timings = true,
105 + .external_irq_controller = true,
106 +
107 + .init_resources = vc5_hdmi_init_resources,
108 + .csc_setup = vc5_hdmi_csc_setup,
109 + .reset = vc5_hdmi_reset,
110 + .set_timings = vc5_hdmi_set_timings,
111 + .phy_init = vc6_hdmi_phy_init,
112 + .phy_disable = vc6_hdmi_phy_disable,
113 + .channel_map = vc5_hdmi_channel_map,
114 + .supports_hdr = true,
115 + .hp_detect = vc5_hdmi_hp_detect,
116 +};
117 +
118 +static const struct vc4_hdmi_variant bcm2712_hdmi1_variant = {
119 + .encoder_type = VC4_ENCODER_TYPE_HDMI1,
120 + .debugfs_name = "hdmi1_regs",
121 + .card_name = "vc4-hdmi-1",
122 + .max_pixel_clock = 600000000,
123 + .registers = vc6_hdmi_hdmi1_fields,
124 + .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi1_fields),
125 + .phy_lane_mapping = {
126 + PHY_LANE_0,
127 + PHY_LANE_1,
128 + PHY_LANE_2,
129 + PHY_LANE_CK,
130 + },
131 + .unsupported_odd_h_timings = true,
132 + .external_irq_controller = true,
133 +
134 + .init_resources = vc5_hdmi_init_resources,
135 + .csc_setup = vc5_hdmi_csc_setup,
136 + .reset = vc5_hdmi_reset,
137 + .set_timings = vc5_hdmi_set_timings,
138 + .phy_init = vc6_hdmi_phy_init,
139 + .phy_disable = vc6_hdmi_phy_disable,
140 + .channel_map = vc5_hdmi_channel_map,
141 + .supports_hdr = true,
142 + .hp_detect = vc5_hdmi_hp_detect,
143 +};
144 +
145 static const struct of_device_id vc4_hdmi_dt_match[] = {
146 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
147 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
148 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
149 + { .compatible = "brcm,bcm2712-hdmi0", .data = &bcm2712_hdmi0_variant },
150 + { .compatible = "brcm,bcm2712-hdmi1", .data = &bcm2712_hdmi1_variant },
151 {}
152 };
153
154 --- a/drivers/gpu/drm/vc4/vc4_hdmi.h
155 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
156 @@ -284,4 +284,8 @@ void vc5_hdmi_phy_disable(struct vc4_hdm
157 void vc5_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi);
158 void vc5_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi);
159
160 +void vc6_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
161 + struct vc4_hdmi_connector_state *vc4_conn_state);
162 +void vc6_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi);
163 +
164 #endif /* _VC4_HDMI_H_ */
165 --- a/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
166 +++ b/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
167 @@ -125,6 +125,48 @@
168 #define VC4_HDMI_RM_FORMAT_SHIFT_SHIFT 24
169 #define VC4_HDMI_RM_FORMAT_SHIFT_MASK VC4_MASK(25, 24)
170
171 +#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_BG_PWRUP BIT(8)
172 +#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_LDO_PWRUP BIT(7)
173 +#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_BIAS_PWRUP BIT(6)
174 +#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_RNDGEN_PWRUP BIT(4)
175 +#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_CK_PWRUP BIT(3)
176 +#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_2_PWRUP BIT(2)
177 +#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_1_PWRUP BIT(1)
178 +#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_0_PWRUP BIT(0)
179 +
180 +#define VC6_HDMI_TX_PHY_PLL_REFCLK_REFCLK_SEL_CMOS BIT(13)
181 +#define VC6_HDMI_TX_PHY_PLL_REFCLK_REFFRQ_MASK VC4_MASK(9, 0)
182 +
183 +#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_CLK0_SEL_MASK VC4_MASK(3, 2)
184 +#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_KDIV_MASK VC4_MASK(1, 0)
185 +
186 +#define VC6_HDMI_TX_PHY_PLL_VCOCLK_DIV_VCODIV_EN BIT(10)
187 +#define VC6_HDMI_TX_PHY_PLL_VCOCLK_DIV_VCODIV_MASK VC4_MASK(9, 0)
188 +
189 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_CTL_MASK VC4_MASK(31, 28)
190 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_ENABLE_MASK VC4_MASK(27, 27)
191 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_RATE_CTL_MASK VC4_MASK(26, 26)
192 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_POST_TAP_EN_MASK VC4_MASK(25, 25)
193 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_LDMOS_BIAS_CTL_MASK VC4_MASK(24, 23)
194 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_COM_MODE_LDMOS_EN_MASK VC4_MASK(22, 22)
195 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EDGE_SEL_MASK VC4_MASK(21, 21)
196 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_HS_EN_MASK VC4_MASK(20, 20)
197 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_TERM_CTL_MASK VC4_MASK(19, 18)
198 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_EN_MASK VC4_MASK(17, 17)
199 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_EN_MASK VC4_MASK(16, 16)
200 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_CTL_MASK VC4_MASK(15, 12)
201 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_HS_EN_MASK VC4_MASK(11, 11)
202 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_MAIN_TAP_CURRENT_SELECT_MASK VC4_MASK(10, 8)
203 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_POST_TAP_CURRENT_SELECT_MASK VC4_MASK(7, 5)
204 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_LOADING_MASK VC4_MASK(4, 3)
205 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_DRIVING_MASK VC4_MASK(2, 1)
206 +#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_PRE_TAP_EN_MASK VC4_MASK(0, 0)
207 +
208 +#define VC6_HDMI_TX_PHY_PLL_RESET_CTL_PLL_PLLPOST_RESETB BIT(1)
209 +#define VC6_HDMI_TX_PHY_PLL_RESET_CTL_PLL_RESETB BIT(0)
210 +
211 +#define VC6_HDMI_TX_PHY_PLL_POWERUP_CTL_PLL_PWRUP BIT(0)
212 +
213 #define OSCILLATOR_FREQUENCY 54000000
214
215 void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
216 @@ -558,3 +600,601 @@ void vc5_hdmi_phy_rng_disable(struct vc4
217 VC4_HDMI_TX_PHY_POWERDOWN_CTL_RNDGEN_PWRDN);
218 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
219 }
220 +
221 +#define VC6_VCO_MIN_FREQ (8ULL * 1000 * 1000 * 1000)
222 +#define VC6_VCO_MAX_FREQ (12ULL * 1000 * 1000 * 1000)
223 +
224 +static unsigned long long
225 +vc6_phy_get_vco_freq(unsigned long long tmds_rate, unsigned int *vco_div)
226 +{
227 + unsigned int min_div;
228 + unsigned int max_div;
229 + unsigned int div;
230 +
231 + div = 0;
232 + while (tmds_rate * div * 10 < VC6_VCO_MIN_FREQ)
233 + div++;
234 + min_div = div;
235 +
236 + while (tmds_rate * (div + 1) * 10 < VC6_VCO_MAX_FREQ)
237 + div++;
238 + max_div = div;
239 +
240 + div = min_div + (max_div - min_div) / 2;
241 +
242 + *vco_div = div;
243 + return tmds_rate * div * 10;
244 +}
245 +
246 +struct vc6_phy_lane_settings {
247 + unsigned int ext_current_ctl:4;
248 + unsigned int ffe_enable:1;
249 + unsigned int slew_rate_ctl:1;
250 + unsigned int ffe_post_tap_en:1;
251 + unsigned int ldmos_bias_ctl:2;
252 + unsigned int com_mode_ldmos_en:1;
253 + unsigned int edge_sel:1;
254 + unsigned int ext_current_src_hs_en:1;
255 + unsigned int term_ctl:2;
256 + unsigned int ext_current_src_en:1;
257 + unsigned int int_current_src_en:1;
258 + unsigned int int_current_ctl:4;
259 + unsigned int int_current_src_hs_en:1;
260 + unsigned int main_tap_current_select:3;
261 + unsigned int post_tap_current_select:3;
262 + unsigned int slew_ctl_slow_loading:2;
263 + unsigned int slew_ctl_slow_driving:2;
264 + unsigned int ffe_pre_tap_en:1;
265 +};
266 +
267 +struct vc6_phy_settings {
268 + unsigned long long min_rate;
269 + unsigned long long max_rate;
270 + struct vc6_phy_lane_settings channel[3];
271 + struct vc6_phy_lane_settings clock;
272 +};
273 +
274 +static const struct vc6_phy_settings vc6_hdmi_phy_settings[] = {
275 + {
276 + 0, 222000000,
277 + {
278 + {
279 + /* 200mA */
280 + .ext_current_ctl = 8,
281 +
282 + /* 0.85V */
283 + .ldmos_bias_ctl = 1,
284 +
285 + /* Enable External Current Source */
286 + .ext_current_src_en = 1,
287 +
288 + /* 200mA */
289 + .int_current_ctl = 8,
290 +
291 + /* 17.6 mA */
292 + .main_tap_current_select = 7,
293 + },
294 + {
295 + /* 200mA */
296 + .ext_current_ctl = 8,
297 +
298 + /* 0.85V */
299 + .ldmos_bias_ctl = 1,
300 +
301 + /* Enable External Current Source */
302 + .ext_current_src_en = 1,
303 +
304 + /* 200mA */
305 + .int_current_ctl = 8,
306 +
307 + /* 17.6 mA */
308 + .main_tap_current_select = 7,
309 + },
310 + {
311 + /* 200mA */
312 + .ext_current_ctl = 8,
313 +
314 + /* 0.85V */
315 + .ldmos_bias_ctl = 1,
316 +
317 + /* Enable External Current Source */
318 + .ext_current_src_en = 1,
319 +
320 + /* 200mA */
321 + .int_current_ctl = 8,
322 +
323 + /* 17.6 mA */
324 + .main_tap_current_select = 7,
325 + },
326 + },
327 + {
328 + /* 200mA */
329 + .ext_current_ctl = 8,
330 +
331 + /* 0.85V */
332 + .ldmos_bias_ctl = 1,
333 +
334 + /* Enable External Current Source */
335 + .ext_current_src_en = 1,
336 +
337 + /* 200mA */
338 + .int_current_ctl = 8,
339 +
340 + /* 17.6 mA */
341 + .main_tap_current_select = 7,
342 + },
343 + },
344 + {
345 + 222000001, 297000000,
346 + {
347 + {
348 + /* 200mA and 180mA ?! */
349 + .ext_current_ctl = 12,
350 +
351 + /* 0.85V */
352 + .ldmos_bias_ctl = 1,
353 +
354 + /* 100 Ohm */
355 + .term_ctl = 1,
356 +
357 + /* Enable External Current Source */
358 + .ext_current_src_en = 1,
359 +
360 + /* Enable Internal Current Source */
361 + .int_current_src_en = 1,
362 + },
363 + {
364 + /* 200mA and 180mA ?! */
365 + .ext_current_ctl = 12,
366 +
367 + /* 0.85V */
368 + .ldmos_bias_ctl = 1,
369 +
370 + /* 100 Ohm */
371 + .term_ctl = 1,
372 +
373 + /* Enable External Current Source */
374 + .ext_current_src_en = 1,
375 +
376 + /* Enable Internal Current Source */
377 + .int_current_src_en = 1,
378 + },
379 + {
380 + /* 200mA and 180mA ?! */
381 + .ext_current_ctl = 12,
382 +
383 + /* 0.85V */
384 + .ldmos_bias_ctl = 1,
385 +
386 + /* 100 Ohm */
387 + .term_ctl = 1,
388 +
389 + /* Enable External Current Source */
390 + .ext_current_src_en = 1,
391 +
392 + /* Enable Internal Current Source */
393 + .int_current_src_en = 1,
394 + },
395 + },
396 + {
397 + /* 200mA and 180mA ?! */
398 + .ext_current_ctl = 12,
399 +
400 + /* 0.85V */
401 + .ldmos_bias_ctl = 1,
402 +
403 + /* 100 Ohm */
404 + .term_ctl = 1,
405 +
406 + /* Enable External Current Source */
407 + .ext_current_src_en = 1,
408 +
409 + /* Enable Internal Current Source */
410 + .int_current_src_en = 1,
411 +
412 + /* Internal Current Source Half Swing Enable*/
413 + .int_current_src_hs_en = 1,
414 + },
415 + },
416 + {
417 + 297000001, 597000044,
418 + {
419 + {
420 + /* 200mA */
421 + .ext_current_ctl = 8,
422 +
423 + /* Normal Slew Rate Control */
424 + .slew_rate_ctl = 1,
425 +
426 + /* 0.85V */
427 + .ldmos_bias_ctl = 1,
428 +
429 + /* 50 Ohms */
430 + .term_ctl = 3,
431 +
432 + /* Enable External Current Source */
433 + .ext_current_src_en = 1,
434 +
435 + /* Enable Internal Current Source */
436 + .int_current_src_en = 1,
437 +
438 + /* 200mA */
439 + .int_current_ctl = 8,
440 +
441 + /* 17.6 mA */
442 + .main_tap_current_select = 7,
443 + },
444 + {
445 + /* 200mA */
446 + .ext_current_ctl = 8,
447 +
448 + /* Normal Slew Rate Control */
449 + .slew_rate_ctl = 1,
450 +
451 + /* 0.85V */
452 + .ldmos_bias_ctl = 1,
453 +
454 + /* 50 Ohms */
455 + .term_ctl = 3,
456 +
457 + /* Enable External Current Source */
458 + .ext_current_src_en = 1,
459 +
460 + /* Enable Internal Current Source */
461 + .int_current_src_en = 1,
462 +
463 + /* 200mA */
464 + .int_current_ctl = 8,
465 +
466 + /* 17.6 mA */
467 + .main_tap_current_select = 7,
468 + },
469 + {
470 + /* 200mA */
471 + .ext_current_ctl = 8,
472 +
473 + /* Normal Slew Rate Control */
474 + .slew_rate_ctl = 1,
475 +
476 + /* 0.85V */
477 + .ldmos_bias_ctl = 1,
478 +
479 + /* 50 Ohms */
480 + .term_ctl = 3,
481 +
482 + /* Enable External Current Source */
483 + .ext_current_src_en = 1,
484 +
485 + /* Enable Internal Current Source */
486 + .int_current_src_en = 1,
487 +
488 + /* 200mA */
489 + .int_current_ctl = 8,
490 +
491 + /* 17.6 mA */
492 + .main_tap_current_select = 7,
493 + },
494 + },
495 + {
496 + /* 200mA */
497 + .ext_current_ctl = 8,
498 +
499 + /* Normal Slew Rate Control */
500 + .slew_rate_ctl = 1,
501 +
502 + /* 0.85V */
503 + .ldmos_bias_ctl = 1,
504 +
505 + /* External Current Source Half Swing Enable*/
506 + .ext_current_src_hs_en = 1,
507 +
508 + /* 50 Ohms */
509 + .term_ctl = 3,
510 +
511 + /* Enable External Current Source */
512 + .ext_current_src_en = 1,
513 +
514 + /* Enable Internal Current Source */
515 + .int_current_src_en = 1,
516 +
517 + /* 200mA */
518 + .int_current_ctl = 8,
519 +
520 + /* Internal Current Source Half Swing Enable*/
521 + .int_current_src_hs_en = 1,
522 +
523 + /* 17.6 mA */
524 + .main_tap_current_select = 7,
525 + },
526 + },
527 +};
528 +
529 +static const struct vc6_phy_settings *
530 +vc6_phy_get_settings(unsigned long long tmds_rate)
531 +{
532 + unsigned int count = ARRAY_SIZE(vc6_hdmi_phy_settings);
533 + unsigned int i;
534 +
535 + for (i = 0; i < count; i++) {
536 + const struct vc6_phy_settings *s = &vc6_hdmi_phy_settings[i];
537 +
538 + if (tmds_rate >= s->min_rate && tmds_rate <= s->max_rate)
539 + return s;
540 + }
541 +
542 + /*
543 + * If the pixel clock exceeds our max setting, try the max
544 + * setting anyway.
545 + */
546 + return &vc6_hdmi_phy_settings[count - 1];
547 +}
548 +
549 +static const struct vc6_phy_lane_settings *
550 +vc6_phy_get_channel_settings(enum vc4_hdmi_phy_channel chan,
551 + unsigned long long tmds_rate)
552 +{
553 + const struct vc6_phy_settings *settings = vc6_phy_get_settings(tmds_rate);
554 +
555 + if (chan == PHY_LANE_CK)
556 + return &settings->clock;
557 +
558 + return &settings->channel[chan];
559 +}
560 +
561 +static void vc6_hdmi_reset_phy(struct vc4_hdmi *vc4_hdmi)
562 +{
563 + lockdep_assert_held(&vc4_hdmi->hw_lock);
564 +
565 + HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0);
566 + HDMI_WRITE(HDMI_TX_PHY_POWERUP_CTL, 0);
567 +}
568 +
569 +void vc6_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
570 + struct vc4_hdmi_connector_state *conn_state)
571 +{
572 + const struct vc6_phy_lane_settings *chan0_settings;
573 + const struct vc6_phy_lane_settings *chan1_settings;
574 + const struct vc6_phy_lane_settings *chan2_settings;
575 + const struct vc6_phy_lane_settings *clock_settings;
576 + const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
577 + unsigned long long pixel_freq = conn_state->tmds_char_rate;
578 + unsigned long long vco_freq;
579 + unsigned char word_sel;
580 + unsigned long flags;
581 + unsigned int vco_div;
582 +
583 + vco_freq = vc6_phy_get_vco_freq(pixel_freq, &vco_div);
584 +
585 + spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
586 +
587 + vc6_hdmi_reset_phy(vc4_hdmi);
588 +
589 + HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_0, 0x810c6000);
590 + HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_1, 0x00b8c451);
591 + HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_2, 0x46402e31);
592 + HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_3, 0x00b8c005);
593 + HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_4, 0x42410261);
594 + HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_5, 0xcc021001);
595 + HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_6, 0xc8301c80);
596 + HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_7, 0xb0804444);
597 + HDMI_WRITE(HDMI_TX_PHY_PLL_MISC_8, 0xf80f8000);
598 +
599 + HDMI_WRITE(HDMI_TX_PHY_PLL_REFCLK,
600 + VC6_HDMI_TX_PHY_PLL_REFCLK_REFCLK_SEL_CMOS |
601 + VC4_SET_FIELD(54, VC6_HDMI_TX_PHY_PLL_REFCLK_REFFRQ));
602 +
603 + HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0x7f);
604 +
605 + HDMI_WRITE(HDMI_RM_OFFSET,
606 + VC4_HDMI_RM_OFFSET_ONLY |
607 + VC4_SET_FIELD(phy_get_rm_offset(vco_freq),
608 + VC4_HDMI_RM_OFFSET_OFFSET));
609 +
610 + HDMI_WRITE(HDMI_TX_PHY_PLL_VCOCLK_DIV,
611 + VC6_HDMI_TX_PHY_PLL_VCOCLK_DIV_VCODIV_EN |
612 + VC4_SET_FIELD(vco_div,
613 + VC6_HDMI_TX_PHY_PLL_VCOCLK_DIV_VCODIV));
614 +
615 + HDMI_WRITE(HDMI_TX_PHY_PLL_CFG,
616 + VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CFG_PDIV));
617 +
618 + HDMI_WRITE(HDMI_TX_PHY_PLL_POST_KDIV,
619 + VC4_SET_FIELD(2, VC6_HDMI_TX_PHY_PLL_POST_KDIV_CLK0_SEL) |
620 + VC4_SET_FIELD(1, VC6_HDMI_TX_PHY_PLL_POST_KDIV_KDIV));
621 +
622 + chan0_settings =
623 + vc6_phy_get_channel_settings(variant->phy_lane_mapping[PHY_LANE_0],
624 + pixel_freq);
625 + HDMI_WRITE(HDMI_TX_PHY_CTL_0,
626 + VC4_SET_FIELD(chan0_settings->ext_current_ctl,
627 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_CTL) |
628 + VC4_SET_FIELD(chan0_settings->ffe_enable,
629 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_ENABLE) |
630 + VC4_SET_FIELD(chan0_settings->slew_rate_ctl,
631 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_RATE_CTL) |
632 + VC4_SET_FIELD(chan0_settings->ffe_post_tap_en,
633 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_POST_TAP_EN) |
634 + VC4_SET_FIELD(chan0_settings->ldmos_bias_ctl,
635 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_LDMOS_BIAS_CTL) |
636 + VC4_SET_FIELD(chan0_settings->com_mode_ldmos_en,
637 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_COM_MODE_LDMOS_EN) |
638 + VC4_SET_FIELD(chan0_settings->edge_sel,
639 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EDGE_SEL) |
640 + VC4_SET_FIELD(chan0_settings->ext_current_src_hs_en,
641 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_HS_EN) |
642 + VC4_SET_FIELD(chan0_settings->term_ctl,
643 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_TERM_CTL) |
644 + VC4_SET_FIELD(chan0_settings->ext_current_src_en,
645 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_EN) |
646 + VC4_SET_FIELD(chan0_settings->int_current_src_en,
647 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_EN) |
648 + VC4_SET_FIELD(chan0_settings->int_current_ctl,
649 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_CTL) |
650 + VC4_SET_FIELD(chan0_settings->int_current_src_hs_en,
651 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_HS_EN) |
652 + VC4_SET_FIELD(chan0_settings->main_tap_current_select,
653 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_MAIN_TAP_CURRENT_SELECT) |
654 + VC4_SET_FIELD(chan0_settings->post_tap_current_select,
655 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_POST_TAP_CURRENT_SELECT) |
656 + VC4_SET_FIELD(chan0_settings->slew_ctl_slow_loading,
657 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_LOADING) |
658 + VC4_SET_FIELD(chan0_settings->slew_ctl_slow_driving,
659 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_DRIVING) |
660 + VC4_SET_FIELD(chan0_settings->ffe_pre_tap_en,
661 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_PRE_TAP_EN));
662 +
663 + chan1_settings =
664 + vc6_phy_get_channel_settings(variant->phy_lane_mapping[PHY_LANE_1],
665 + pixel_freq);
666 + HDMI_WRITE(HDMI_TX_PHY_CTL_1,
667 + VC4_SET_FIELD(chan1_settings->ext_current_ctl,
668 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_CTL) |
669 + VC4_SET_FIELD(chan1_settings->ffe_enable,
670 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_ENABLE) |
671 + VC4_SET_FIELD(chan1_settings->slew_rate_ctl,
672 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_RATE_CTL) |
673 + VC4_SET_FIELD(chan1_settings->ffe_post_tap_en,
674 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_POST_TAP_EN) |
675 + VC4_SET_FIELD(chan1_settings->ldmos_bias_ctl,
676 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_LDMOS_BIAS_CTL) |
677 + VC4_SET_FIELD(chan1_settings->com_mode_ldmos_en,
678 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_COM_MODE_LDMOS_EN) |
679 + VC4_SET_FIELD(chan1_settings->edge_sel,
680 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EDGE_SEL) |
681 + VC4_SET_FIELD(chan1_settings->ext_current_src_hs_en,
682 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_HS_EN) |
683 + VC4_SET_FIELD(chan1_settings->term_ctl,
684 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_TERM_CTL) |
685 + VC4_SET_FIELD(chan1_settings->ext_current_src_en,
686 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_EN) |
687 + VC4_SET_FIELD(chan1_settings->int_current_src_en,
688 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_EN) |
689 + VC4_SET_FIELD(chan1_settings->int_current_ctl,
690 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_CTL) |
691 + VC4_SET_FIELD(chan1_settings->int_current_src_hs_en,
692 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_HS_EN) |
693 + VC4_SET_FIELD(chan1_settings->main_tap_current_select,
694 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_MAIN_TAP_CURRENT_SELECT) |
695 + VC4_SET_FIELD(chan1_settings->post_tap_current_select,
696 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_POST_TAP_CURRENT_SELECT) |
697 + VC4_SET_FIELD(chan1_settings->slew_ctl_slow_loading,
698 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_LOADING) |
699 + VC4_SET_FIELD(chan1_settings->slew_ctl_slow_driving,
700 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_DRIVING) |
701 + VC4_SET_FIELD(chan1_settings->ffe_pre_tap_en,
702 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_PRE_TAP_EN));
703 +
704 + chan2_settings =
705 + vc6_phy_get_channel_settings(variant->phy_lane_mapping[PHY_LANE_2],
706 + pixel_freq);
707 + HDMI_WRITE(HDMI_TX_PHY_CTL_2,
708 + VC4_SET_FIELD(chan2_settings->ext_current_ctl,
709 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_CTL) |
710 + VC4_SET_FIELD(chan2_settings->ffe_enable,
711 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_ENABLE) |
712 + VC4_SET_FIELD(chan2_settings->slew_rate_ctl,
713 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_RATE_CTL) |
714 + VC4_SET_FIELD(chan2_settings->ffe_post_tap_en,
715 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_POST_TAP_EN) |
716 + VC4_SET_FIELD(chan2_settings->ldmos_bias_ctl,
717 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_LDMOS_BIAS_CTL) |
718 + VC4_SET_FIELD(chan2_settings->com_mode_ldmos_en,
719 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_COM_MODE_LDMOS_EN) |
720 + VC4_SET_FIELD(chan2_settings->edge_sel,
721 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EDGE_SEL) |
722 + VC4_SET_FIELD(chan2_settings->ext_current_src_hs_en,
723 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_HS_EN) |
724 + VC4_SET_FIELD(chan2_settings->term_ctl,
725 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_TERM_CTL) |
726 + VC4_SET_FIELD(chan2_settings->ext_current_src_en,
727 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_EN) |
728 + VC4_SET_FIELD(chan2_settings->int_current_src_en,
729 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_EN) |
730 + VC4_SET_FIELD(chan2_settings->int_current_ctl,
731 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_CTL) |
732 + VC4_SET_FIELD(chan2_settings->int_current_src_hs_en,
733 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_HS_EN) |
734 + VC4_SET_FIELD(chan2_settings->main_tap_current_select,
735 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_MAIN_TAP_CURRENT_SELECT) |
736 + VC4_SET_FIELD(chan2_settings->post_tap_current_select,
737 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_POST_TAP_CURRENT_SELECT) |
738 + VC4_SET_FIELD(chan2_settings->slew_ctl_slow_loading,
739 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_LOADING) |
740 + VC4_SET_FIELD(chan2_settings->slew_ctl_slow_driving,
741 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_DRIVING) |
742 + VC4_SET_FIELD(chan2_settings->ffe_pre_tap_en,
743 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_PRE_TAP_EN));
744 +
745 + clock_settings =
746 + vc6_phy_get_channel_settings(variant->phy_lane_mapping[PHY_LANE_CK],
747 + pixel_freq);
748 + HDMI_WRITE(HDMI_TX_PHY_CTL_CK,
749 + VC4_SET_FIELD(clock_settings->ext_current_ctl,
750 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_CTL) |
751 + VC4_SET_FIELD(clock_settings->ffe_enable,
752 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_ENABLE) |
753 + VC4_SET_FIELD(clock_settings->slew_rate_ctl,
754 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_RATE_CTL) |
755 + VC4_SET_FIELD(clock_settings->ffe_post_tap_en,
756 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_POST_TAP_EN) |
757 + VC4_SET_FIELD(clock_settings->ldmos_bias_ctl,
758 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_LDMOS_BIAS_CTL) |
759 + VC4_SET_FIELD(clock_settings->com_mode_ldmos_en,
760 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_COM_MODE_LDMOS_EN) |
761 + VC4_SET_FIELD(clock_settings->edge_sel,
762 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EDGE_SEL) |
763 + VC4_SET_FIELD(clock_settings->ext_current_src_hs_en,
764 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_HS_EN) |
765 + VC4_SET_FIELD(clock_settings->term_ctl,
766 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_TERM_CTL) |
767 + VC4_SET_FIELD(clock_settings->ext_current_src_en,
768 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_EN) |
769 + VC4_SET_FIELD(clock_settings->int_current_src_en,
770 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_EN) |
771 + VC4_SET_FIELD(clock_settings->int_current_ctl,
772 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_CTL) |
773 + VC4_SET_FIELD(clock_settings->int_current_src_hs_en,
774 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_HS_EN) |
775 + VC4_SET_FIELD(clock_settings->main_tap_current_select,
776 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_MAIN_TAP_CURRENT_SELECT) |
777 + VC4_SET_FIELD(clock_settings->post_tap_current_select,
778 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_POST_TAP_CURRENT_SELECT) |
779 + VC4_SET_FIELD(clock_settings->slew_ctl_slow_loading,
780 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_LOADING) |
781 + VC4_SET_FIELD(clock_settings->slew_ctl_slow_driving,
782 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_DRIVING) |
783 + VC4_SET_FIELD(clock_settings->ffe_pre_tap_en,
784 + VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_PRE_TAP_EN));
785 +
786 + if (pixel_freq >= 340000000)
787 + word_sel = 3;
788 + else
789 + word_sel = 0;
790 + HDMI_WRITE(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, word_sel);
791 +
792 + HDMI_WRITE(HDMI_TX_PHY_POWERUP_CTL,
793 + VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_BG_PWRUP |
794 + VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_LDO_PWRUP |
795 + VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_BIAS_PWRUP |
796 + VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_CK_PWRUP |
797 + VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_2_PWRUP |
798 + VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_1_PWRUP |
799 + VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_0_PWRUP);
800 +
801 + HDMI_WRITE(HDMI_TX_PHY_PLL_POWERUP_CTL,
802 + VC6_HDMI_TX_PHY_PLL_POWERUP_CTL_PLL_PWRUP);
803 +
804 + HDMI_WRITE(HDMI_TX_PHY_PLL_RESET_CTL,
805 + HDMI_READ(HDMI_TX_PHY_PLL_RESET_CTL) &
806 + ~VC6_HDMI_TX_PHY_PLL_RESET_CTL_PLL_RESETB);
807 +
808 + HDMI_WRITE(HDMI_TX_PHY_PLL_RESET_CTL,
809 + HDMI_READ(HDMI_TX_PHY_PLL_RESET_CTL) |
810 + VC6_HDMI_TX_PHY_PLL_RESET_CTL_PLL_RESETB);
811 +
812 + spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
813 +}
814 +
815 +void vc6_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi)
816 +{
817 +}
818 --- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
819 +++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
820 @@ -111,13 +111,30 @@ enum vc4_hdmi_field {
821 HDMI_TX_PHY_CTL_1,
822 HDMI_TX_PHY_CTL_2,
823 HDMI_TX_PHY_CTL_3,
824 + HDMI_TX_PHY_CTL_CK,
825 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1,
826 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2,
827 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4,
828 HDMI_TX_PHY_PLL_CFG,
829 + HDMI_TX_PHY_PLL_CFG_PDIV,
830 HDMI_TX_PHY_PLL_CTL_0,
831 HDMI_TX_PHY_PLL_CTL_1,
832 + HDMI_TX_PHY_PLL_MISC_0,
833 + HDMI_TX_PHY_PLL_MISC_1,
834 + HDMI_TX_PHY_PLL_MISC_2,
835 + HDMI_TX_PHY_PLL_MISC_3,
836 + HDMI_TX_PHY_PLL_MISC_4,
837 + HDMI_TX_PHY_PLL_MISC_5,
838 + HDMI_TX_PHY_PLL_MISC_6,
839 + HDMI_TX_PHY_PLL_MISC_7,
840 + HDMI_TX_PHY_PLL_MISC_8,
841 + HDMI_TX_PHY_PLL_POST_KDIV,
842 + HDMI_TX_PHY_PLL_POWERUP_CTL,
843 + HDMI_TX_PHY_PLL_REFCLK,
844 + HDMI_TX_PHY_PLL_RESET_CTL,
845 + HDMI_TX_PHY_PLL_VCOCLK_DIV,
846 HDMI_TX_PHY_POWERDOWN_CTL,
847 + HDMI_TX_PHY_POWERUP_CTL,
848 HDMI_TX_PHY_RESET_CTL,
849 HDMI_TX_PHY_TMDS_CLK_WORD_SEL,
850 HDMI_VEC_INTERFACE_CFG,
851 @@ -383,6 +400,206 @@ static const struct vc4_hdmi_register __
852
853 VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
854 VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
855 + VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
856 +
857 + VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
858 +
859 + VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
860 + VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
861 + VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
862 + VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
863 + VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
864 + VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
865 + VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
866 + VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
867 + VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
868 + VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
869 + VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
870 + VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
871 + VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
872 +
873 + VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
874 + VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
875 + VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
876 + VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
877 + VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
878 + VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
879 + VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
880 + VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
881 +};
882 +
883 +static const struct vc4_hdmi_register __maybe_unused vc6_hdmi_hdmi0_fields[] = {
884 + VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
885 + VC4_HD_REG(HDMI_MAI_CTL, 0x0010),
886 + VC4_HD_REG(HDMI_MAI_THR, 0x0014),
887 + VC4_HD_REG(HDMI_MAI_FMT, 0x0018),
888 + VC4_HD_REG(HDMI_MAI_DATA, 0x001c),
889 + VC4_HD_REG(HDMI_MAI_SMP, 0x0020),
890 + VC4_HD_REG(HDMI_VID_CTL, 0x0044),
891 + VC4_HD_REG(HDMI_FRAME_COUNT, 0x0060),
892 +
893 + VC4_HDMI_REG(HDMI_FIFO_CTL, 0x07c),
894 + VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0c0),
895 + VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0c4),
896 + VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0cc),
897 + VC4_HDMI_REG(HDMI_CRP_CFG, 0x0d0),
898 + VC4_HDMI_REG(HDMI_CTS_0, 0x0d4),
899 + VC4_HDMI_REG(HDMI_CTS_1, 0x0d8),
900 + VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e8),
901 + VC4_HDMI_REG(HDMI_HORZA, 0x0ec),
902 + VC4_HDMI_REG(HDMI_HORZB, 0x0f0),
903 + VC4_HDMI_REG(HDMI_VERTA0, 0x0f4),
904 + VC4_HDMI_REG(HDMI_VERTB0, 0x0f8),
905 + VC4_HDMI_REG(HDMI_VERTA1, 0x100),
906 + VC4_HDMI_REG(HDMI_VERTB1, 0x104),
907 + VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x114),
908 + VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0a4),
909 + VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a8),
910 + VC4_HDMI_REG(HDMI_FORMAT_DET_1, 0x148),
911 + VC4_HDMI_REG(HDMI_FORMAT_DET_2, 0x14c),
912 + VC4_HDMI_REG(HDMI_FORMAT_DET_3, 0x150),
913 + VC4_HDMI_REG(HDMI_FORMAT_DET_4, 0x158),
914 + VC4_HDMI_REG(HDMI_FORMAT_DET_5, 0x15c),
915 + VC4_HDMI_REG(HDMI_FORMAT_DET_6, 0x160),
916 + VC4_HDMI_REG(HDMI_FORMAT_DET_7, 0x164),
917 + VC4_HDMI_REG(HDMI_FORMAT_DET_8, 0x168),
918 + VC4_HDMI_REG(HDMI_FORMAT_DET_9, 0x16c),
919 + VC4_HDMI_REG(HDMI_FORMAT_DET_10, 0x170),
920 + VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x18c),
921 + VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x194),
922 + VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x198),
923 + VC4_HDMI_REG(HDMI_HOTPLUG, 0x1c8),
924 + VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1e4),
925 +
926 + VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
927 + VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0f0),
928 + VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f4),
929 +
930 + VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
931 + VC5_PHY_REG(HDMI_TX_PHY_POWERUP_CTL, 0x004),
932 + VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
933 + VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
934 + VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
935 + VC5_PHY_REG(HDMI_TX_PHY_CTL_CK, 0x014),
936 + VC5_PHY_REG(HDMI_TX_PHY_PLL_REFCLK, 0x01c),
937 + VC5_PHY_REG(HDMI_TX_PHY_PLL_POST_KDIV, 0x028),
938 + VC5_PHY_REG(HDMI_TX_PHY_PLL_VCOCLK_DIV, 0x02c),
939 + VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x044),
940 + VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x054),
941 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_0, 0x060),
942 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_1, 0x064),
943 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_2, 0x068),
944 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_3, 0x06c),
945 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_4, 0x070),
946 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_5, 0x074),
947 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_6, 0x078),
948 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_7, 0x07c),
949 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_8, 0x080),
950 + VC5_PHY_REG(HDMI_TX_PHY_PLL_RESET_CTL, 0x190),
951 + VC5_PHY_REG(HDMI_TX_PHY_PLL_POWERUP_CTL, 0x194),
952 +
953 + VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
954 + VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
955 + VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
956 +
957 + VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
958 +
959 + VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
960 + VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
961 + VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
962 + VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
963 + VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
964 + VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
965 + VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
966 + VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
967 + VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
968 + VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
969 + VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
970 + VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
971 + VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
972 +
973 + VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
974 + VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
975 + VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
976 + VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
977 + VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
978 + VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
979 + VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
980 + VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
981 +};
982 +
983 +static const struct vc4_hdmi_register __maybe_unused vc6_hdmi_hdmi1_fields[] = {
984 + VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
985 + VC4_HD_REG(HDMI_MAI_CTL, 0x0030),
986 + VC4_HD_REG(HDMI_MAI_THR, 0x0034),
987 + VC4_HD_REG(HDMI_MAI_FMT, 0x0038),
988 + VC4_HD_REG(HDMI_MAI_DATA, 0x003c),
989 + VC4_HD_REG(HDMI_MAI_SMP, 0x0040),
990 + VC4_HD_REG(HDMI_VID_CTL, 0x0048),
991 + VC4_HD_REG(HDMI_FRAME_COUNT, 0x0064),
992 +
993 + VC4_HDMI_REG(HDMI_FIFO_CTL, 0x07c),
994 + VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0c0),
995 + VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0c4),
996 + VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0cc),
997 + VC4_HDMI_REG(HDMI_CRP_CFG, 0x0d0),
998 + VC4_HDMI_REG(HDMI_CTS_0, 0x0d4),
999 + VC4_HDMI_REG(HDMI_CTS_1, 0x0d8),
1000 + VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e8),
1001 + VC4_HDMI_REG(HDMI_HORZA, 0x0ec),
1002 + VC4_HDMI_REG(HDMI_HORZB, 0x0f0),
1003 + VC4_HDMI_REG(HDMI_VERTA0, 0x0f4),
1004 + VC4_HDMI_REG(HDMI_VERTB0, 0x0f8),
1005 + VC4_HDMI_REG(HDMI_VERTA1, 0x100),
1006 + VC4_HDMI_REG(HDMI_VERTB1, 0x104),
1007 + VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x114),
1008 + VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0a4),
1009 + VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a8),
1010 + VC4_HDMI_REG(HDMI_FORMAT_DET_1, 0x148),
1011 + VC4_HDMI_REG(HDMI_FORMAT_DET_2, 0x14c),
1012 + VC4_HDMI_REG(HDMI_FORMAT_DET_3, 0x150),
1013 + VC4_HDMI_REG(HDMI_FORMAT_DET_4, 0x158),
1014 + VC4_HDMI_REG(HDMI_FORMAT_DET_5, 0x15c),
1015 + VC4_HDMI_REG(HDMI_FORMAT_DET_6, 0x160),
1016 + VC4_HDMI_REG(HDMI_FORMAT_DET_7, 0x164),
1017 + VC4_HDMI_REG(HDMI_FORMAT_DET_8, 0x168),
1018 + VC4_HDMI_REG(HDMI_FORMAT_DET_9, 0x16c),
1019 + VC4_HDMI_REG(HDMI_FORMAT_DET_10, 0x170),
1020 + VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x18c),
1021 + VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x194),
1022 + VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x198),
1023 + VC4_HDMI_REG(HDMI_HOTPLUG, 0x1c8),
1024 + VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1e4),
1025 +
1026 + VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
1027 + VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0f0),
1028 + VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f4),
1029 +
1030 + VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
1031 + VC5_PHY_REG(HDMI_TX_PHY_POWERUP_CTL, 0x004),
1032 + VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
1033 + VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
1034 + VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
1035 + VC5_PHY_REG(HDMI_TX_PHY_CTL_CK, 0x014),
1036 + VC5_PHY_REG(HDMI_TX_PHY_PLL_REFCLK, 0x01c),
1037 + VC5_PHY_REG(HDMI_TX_PHY_PLL_POST_KDIV, 0x028),
1038 + VC5_PHY_REG(HDMI_TX_PHY_PLL_VCOCLK_DIV, 0x02c),
1039 + VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x044),
1040 + VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x054),
1041 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_0, 0x060),
1042 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_1, 0x064),
1043 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_2, 0x068),
1044 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_3, 0x06c),
1045 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_4, 0x070),
1046 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_5, 0x074),
1047 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_6, 0x078),
1048 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_7, 0x07c),
1049 + VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_8, 0x080),
1050 + VC5_PHY_REG(HDMI_TX_PHY_PLL_RESET_CTL, 0x190),
1051 + VC5_PHY_REG(HDMI_TX_PHY_PLL_POWERUP_CTL, 0x194),
1052 +
1053 + VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
1054 + VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
1055 VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
1056
1057 VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
Staging tree of Matthias Schiffer