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   1 From 2e4c0c429526d88b96319d7bb08c51bfa70f6e27 Mon Sep 17 00:00:00 2001
   2 From: Bhupesh Sharma <bhsharma@redhat.com>
   3 Date: Fri, 29 Nov 2019 01:55:13 +0530
   4 Subject: [PATCH] LF-419 arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo
   5
   6 vabits_actual variable on arm64 indicates the actual VA space size,
   7 and allows a single binary to support both 48-bit and 52-bit VA
   8 spaces.
   9
  10 If the ARMv8.2-LVA optional feature is present, and we are running
  11 with a 64KB page size; then it is possible to use 52-bits of address
  12 space for both userspace and kernel addresses. However, any kernel
  13 binary that supports 52-bit must also be able to fall back to 48-bit
  14 at early boot time if the hardware feature is not present.
  15
  16 Since TCR_EL1.T1SZ indicates the size offset of the memory region
  17 addressed by TTBR1_EL1 (and hence can be used for determining the
  18 vabits_actual value) it makes more sense to export the same in
  19 vmcoreinfo rather than vabits_actual variable, as the name of the
  20 variable can change in future kernel versions, but the architectural
  21 constructs like TCR_EL1.T1SZ can be used better to indicate intended
  22 specific fields to user-space.
  23
  24 User-space utilities like makedumpfile and crash-utility, need to
  25 read/write this value from/to vmcoreinfo for determining if a virtual
  26 address lies in the linear map range.
  27
  28 The user-space computation for determining whether an address lies in
  29 the linear map range is the same as we have in kernel-space:
  30
  31   #define __is_lm_address(addr) (!(((u64)addr) & BIT(vabits_actual - 1)))
  32
  33 I have sent out user-space patches for makedumpfile and crash-utility
  34 to add features for obtaining vabits_actual value from TCR_EL1.T1SZ (see
  35 [0] and [1]).
  36
  37 Akashi reported that he was able to use this patchset and the user-space
  38 changes to get user-space working fine with the 52-bit kernel VA
  39 changes (see [2]).
  40
  41 [0]. http://lists.infradead.org/pipermail/kexec/2019-November/023966.html
  42 [1]. http://lists.infradead.org/pipermail/kexec/2019-November/024006.html
  43 [2]. http://lists.infradead.org/pipermail/kexec/2019-November/023992.html
  44
  45 Cc: James Morse <james.morse@arm.com>
  46 Cc: Mark Rutland <mark.rutland@arm.com>
  47 Cc: Will Deacon <will@kernel.org>
  48 Cc: Steve Capper <steve.capper@arm.com>
  49 Cc: Catalin Marinas <catalin.marinas@arm.com>
  50 Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
  51 Cc: Dave Anderson <anderson@redhat.com>
  52 Cc: Kazuhito Hagio <k-hagio@ab.jp.nec.com>
  53 Cc: linux-arm-kernel@lists.infradead.org
  54 Cc: linux-kernel@vger.kernel.org
  55 Cc: kexec@lists.infradead.org
  56 Signed-off-by: Bhupesh Sharma <bhsharma@redhat.com>
  57 Tested-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
  58 Acked-by: Li Yang <leoyang.li@nxp.com>
  59 ---
  60  arch/arm64/include/asm/pgtable-hwdef.h | 1 +
  61  arch/arm64/kernel/crash_core.c         | 9 +++++++++
  62  2 files changed, 10 insertions(+)
  63
  64 --- a/arch/arm64/include/asm/pgtable-hwdef.h
  65 +++ b/arch/arm64/include/asm/pgtable-hwdef.h
  66 @@ -215,6 +215,7 @@
  67  #define TCR_TxSZ(x)            (TCR_T0SZ(x) | TCR_T1SZ(x))
  68  #define TCR_TxSZ_WIDTH         6
  69  #define TCR_T0SZ_MASK          (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
  70 +#define TCR_T1SZ_MASK          (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
  71
  72  #define TCR_EPD0_SHIFT         7
  73  #define TCR_EPD0_MASK          (UL(1) << TCR_EPD0_SHIFT)
  74 --- a/arch/arm64/kernel/crash_core.c
  75 +++ b/arch/arm64/kernel/crash_core.c
  76 @@ -7,6 +7,13 @@
  77  #include <linux/crash_core.h>
  78  #include <asm/memory.h>
  79
  80 +static inline u64 get_tcr_el1_t1sz(void);
  81 +
  82 +static inline u64 get_tcr_el1_t1sz(void)
  83 +{
  84 +       return (read_sysreg(tcr_el1) & TCR_T1SZ_MASK) >> TCR_T1SZ_OFFSET;
  85 +}
  86 +
  87  void arch_crash_save_vmcoreinfo(void)
  88  {
  89         VMCOREINFO_NUMBER(VA_BITS);
  90 @@ -15,5 +22,7 @@ void arch_crash_save_vmcoreinfo(void)
  91                                                 kimage_voffset);
  92         vmcoreinfo_append_str("NUMBER(PHYS_OFFSET)=0x%llx\n",
  93                                                 PHYS_OFFSET);
  94 +       vmcoreinfo_append_str("NUMBER(tcr_el1_t1sz)=0x%llx\n",
  95 +                                               get_tcr_el1_t1sz());
  96         vmcoreinfo_append_str("KERNELOFFSET=%lx\n", kaslr_offset());
  97  }