git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From 13bcdf07cb2ecff5d45d2c141df2539b15211448 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
   3 Date: Tue, 30 Nov 2021 18:29:09 +0100
   4 Subject: [PATCH] PCI: aardvark: Mask all interrupts when unbinding driver
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
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   8
   9 Ensure that no interrupt can be triggered after driver unbind.
  10
  11 Link: https://lore.kernel.org/r/20211130172913.9727-8-kabel@kernel.org
  12 Signed-off-by: Pali Rohár <pali@kernel.org>
  13 Signed-off-by: Marek Behún <kabel@kernel.org>
  14 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  15 ---
  16  drivers/pci/controller/pci-aardvark.c | 21 +++++++++++++++++++++
  17  1 file changed, 21 insertions(+)
  18
  19 --- a/drivers/pci/controller/pci-aardvark.c
  20 +++ b/drivers/pci/controller/pci-aardvark.c
  21 @@ -1710,6 +1710,27 @@ static int advk_pcie_remove(struct platf
  22         val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  23         advk_writel(pcie, val, PCIE_CORE_CMD_STATUS_REG);
  24
  25 +       /* Disable MSI */
  26 +       val = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
  27 +       val &= ~PCIE_CORE_CTRL2_MSI_ENABLE;
  28 +       advk_writel(pcie, val, PCIE_CORE_CTRL2_REG);
  29 +
  30 +       /* Clear MSI address */
  31 +       advk_writel(pcie, 0, PCIE_MSI_ADDR_LOW_REG);
  32 +       advk_writel(pcie, 0, PCIE_MSI_ADDR_HIGH_REG);
  33 +
  34 +       /* Mask all interrupts */
  35 +       advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
  36 +       advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);
  37 +       advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
  38 +       advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_MASK_REG);
  39 +
  40 +       /* Clear all interrupts */
  41 +       advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
  42 +       advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
  43 +       advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
  44 +       advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
  45 +
  46         /* Remove IRQ domains */
  47         advk_pcie_remove_msi_irq_domain(pcie);
  48         advk_pcie_remove_irq_domain(pcie);