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1 From c57e558194430d10d5e5f4acd8a8655b68dade13 Mon Sep 17 00:00:00 2001
2 From: Frank Wunderlich <frank-w@public-files.de>
3 Date: Mon, 3 Jun 2024 21:25:05 +0200
4 Subject: [PATCH] net: ethernet: mtk_eth_soc: handle dma buffer size soc
5 specific
6
7 The mainline MTK ethernet driver suffers long time from rarly but
8 annoying tx queue timeouts. We think that this is caused by fixed
9 dma sizes hardcoded for all SoCs.
10
11 We suspect this problem arises from a low level of free TX DMADs,
12 the TX Ring alomost full.
13
14 The transmit timeout is caused by the Tx queue not waking up. The
15 Tx queue stops when the free counter is less than ring->thres, and
16 it will wake up once the free counter is greater than ring->thres.
17 If the CPU is too late to wake up the Tx queues, it may cause a
18 transmit timeout.
19 Therefore, we increased the TX and RX DMADs to improve this error
20 situation.
21
22 Use the dma-size implementation from SDK in a per SoC manner. In
23 difference to SDK we have no RSS feature yet, so all RX/TX sizes
24 should be raised from 512 to 2048 byte except fqdma on mt7988 to
25 avoid the tx timeout issue.
26
27 Fixes: 656e705243fd ("net-next: mediatek: add support for MT7623 ethernet")
28 Suggested-by: Daniel Golle <daniel@makrotopia.org>
29 Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
30 Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
31 Signed-off-by: David S. Miller <davem@davemloft.net>
32 ---
33 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 104 +++++++++++++-------
34 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 9 +-
35 2 files changed, 77 insertions(+), 36 deletions(-)
36
37 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
38 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
39 @@ -1071,9 +1071,9 @@ static int mtk_init_fq_dma(struct mtk_et
40 {
41 const struct mtk_soc_data *soc = eth->soc;
42 dma_addr_t phy_ring_tail;
43 - int cnt = MTK_QDMA_RING_SIZE;
44 + int cnt = soc->tx.fq_dma_size;
45 dma_addr_t dma_addr;
46 - int i;
47 + int i, j, len;
48
49 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM))
50 eth->scratch_ring = eth->sram_base;
51 @@ -1082,40 +1082,46 @@ static int mtk_init_fq_dma(struct mtk_et
52 cnt * soc->tx.desc_size,
53 &eth->phy_scratch_ring,
54 GFP_KERNEL);
55 +
56 if (unlikely(!eth->scratch_ring))
57 return -ENOMEM;
58
59 - eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL);
60 - if (unlikely(!eth->scratch_head))
61 - return -ENOMEM;
62 + phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1);
63
64 - dma_addr = dma_map_single(eth->dma_dev,
65 - eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
66 - DMA_FROM_DEVICE);
67 - if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
68 - return -ENOMEM;
69 + for (j = 0; j < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); j++) {
70 + len = min_t(int, cnt - j * MTK_FQ_DMA_LENGTH, MTK_FQ_DMA_LENGTH);
71 + eth->scratch_head[j] = kcalloc(len, MTK_QDMA_PAGE_SIZE, GFP_KERNEL);
72
73 - phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1);
74 + if (unlikely(!eth->scratch_head[j]))
75 + return -ENOMEM;
76
77 - for (i = 0; i < cnt; i++) {
78 - dma_addr_t addr = dma_addr + i * MTK_QDMA_PAGE_SIZE;
79 - struct mtk_tx_dma_v2 *txd;
80 -
81 - txd = eth->scratch_ring + i * soc->tx.desc_size;
82 - txd->txd1 = addr;
83 - if (i < cnt - 1)
84 - txd->txd2 = eth->phy_scratch_ring +
85 - (i + 1) * soc->tx.desc_size;
86 -
87 - txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
88 - if (MTK_HAS_CAPS(soc->caps, MTK_36BIT_DMA))
89 - txd->txd3 |= TX_DMA_PREP_ADDR64(addr);
90 - txd->txd4 = 0;
91 - if (mtk_is_netsys_v2_or_greater(eth)) {
92 - txd->txd5 = 0;
93 - txd->txd6 = 0;
94 - txd->txd7 = 0;
95 - txd->txd8 = 0;
96 + dma_addr = dma_map_single(eth->dma_dev,
97 + eth->scratch_head[j], len * MTK_QDMA_PAGE_SIZE,
98 + DMA_FROM_DEVICE);
99 +
100 + if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
101 + return -ENOMEM;
102 +
103 + for (i = 0; i < cnt; i++) {
104 + struct mtk_tx_dma_v2 *txd;
105 +
106 + txd = eth->scratch_ring + (j * MTK_FQ_DMA_LENGTH + i) * soc->tx.desc_size;
107 + txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
108 + if (j * MTK_FQ_DMA_LENGTH + i < cnt)
109 + txd->txd2 = eth->phy_scratch_ring +
110 + (j * MTK_FQ_DMA_LENGTH + i + 1) * soc->tx.desc_size;
111 +
112 + txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
113 + if (MTK_HAS_CAPS(soc->caps, MTK_36BIT_DMA))
114 + txd->txd3 |= TX_DMA_PREP_ADDR64(dma_addr + i * MTK_QDMA_PAGE_SIZE);
115 +
116 + txd->txd4 = 0;
117 + if (mtk_is_netsys_v2_or_greater(eth)) {
118 + txd->txd5 = 0;
119 + txd->txd6 = 0;
120 + txd->txd7 = 0;
121 + txd->txd8 = 0;
122 + }
123 }
124 }
125
126 @@ -2386,7 +2392,7 @@ static int mtk_tx_alloc(struct mtk_eth *
127 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA))
128 ring_size = MTK_QDMA_RING_SIZE;
129 else
130 - ring_size = MTK_DMA_SIZE;
131 + ring_size = soc->tx.dma_size;
132
133 ring->buf = kcalloc(ring_size, sizeof(*ring->buf),
134 GFP_KERNEL);
135 @@ -2394,8 +2400,8 @@ static int mtk_tx_alloc(struct mtk_eth *
136 goto no_tx_mem;
137
138 if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) {
139 - ring->dma = eth->sram_base + ring_size * sz;
140 - ring->phys = eth->phy_scratch_ring + ring_size * (dma_addr_t)sz;
141 + ring->dma = eth->sram_base + soc->tx.fq_dma_size * sz;
142 + ring->phys = eth->phy_scratch_ring + soc->tx.fq_dma_size * (dma_addr_t)sz;
143 } else {
144 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
145 &ring->phys, GFP_KERNEL);
146 @@ -2517,6 +2523,7 @@ static void mtk_tx_clean(struct mtk_eth
147 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
148 {
149 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
150 + const struct mtk_soc_data *soc = eth->soc;
151 struct mtk_rx_ring *ring;
152 int rx_data_len, rx_dma_size, tx_ring_size;
153 int i;
154 @@ -2524,7 +2531,7 @@ static int mtk_rx_alloc(struct mtk_eth *
155 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
156 tx_ring_size = MTK_QDMA_RING_SIZE;
157 else
158 - tx_ring_size = MTK_DMA_SIZE;
159 + tx_ring_size = soc->tx.dma_size;
160
161 if (rx_flag == MTK_RX_FLAGS_QDMA) {
162 if (ring_no)
163 @@ -2539,7 +2546,7 @@ static int mtk_rx_alloc(struct mtk_eth *
164 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
165 } else {
166 rx_data_len = ETH_DATA_LEN;
167 - rx_dma_size = MTK_DMA_SIZE;
168 + rx_dma_size = soc->rx.dma_size;
169 }
170
171 ring->frag_size = mtk_max_frag_size(rx_data_len);
172 @@ -3066,7 +3073,10 @@ static void mtk_dma_free(struct mtk_eth
173 mtk_rx_clean(eth, &eth->rx_ring[i], false);
174 }
175
176 - kfree(eth->scratch_head);
177 + for (i = 0; i < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); i++) {
178 + kfree(eth->scratch_head[i]);
179 + eth->scratch_head[i] = NULL;
180 + }
181 }
182
183 static bool mtk_hw_reset_check(struct mtk_eth *eth)
184 @@ -4952,11 +4962,14 @@ static const struct mtk_soc_data mt2701_
185 .desc_size = sizeof(struct mtk_tx_dma),
186 .dma_max_len = MTK_TX_DMA_BUF_LEN,
187 .dma_len_offset = 16,
188 + .dma_size = MTK_DMA_SIZE(2K),
189 + .fq_dma_size = MTK_DMA_SIZE(2K),
190 },
191 .rx = {
192 .desc_size = sizeof(struct mtk_rx_dma),
193 .irq_done_mask = MTK_RX_DONE_INT,
194 .dma_l4_valid = RX_DMA_L4_VALID,
195 + .dma_size = MTK_DMA_SIZE(2K),
196 .dma_max_len = MTK_TX_DMA_BUF_LEN,
197 .dma_len_offset = 16,
198 },
199 @@ -4976,11 +4989,14 @@ static const struct mtk_soc_data mt7621_
200 .desc_size = sizeof(struct mtk_tx_dma),
201 .dma_max_len = MTK_TX_DMA_BUF_LEN,
202 .dma_len_offset = 16,
203 + .dma_size = MTK_DMA_SIZE(2K),
204 + .fq_dma_size = MTK_DMA_SIZE(2K),
205 },
206 .rx = {
207 .desc_size = sizeof(struct mtk_rx_dma),
208 .irq_done_mask = MTK_RX_DONE_INT,
209 .dma_l4_valid = RX_DMA_L4_VALID,
210 + .dma_size = MTK_DMA_SIZE(2K),
211 .dma_max_len = MTK_TX_DMA_BUF_LEN,
212 .dma_len_offset = 16,
213 },
214 @@ -5002,11 +5018,14 @@ static const struct mtk_soc_data mt7622_
215 .desc_size = sizeof(struct mtk_tx_dma),
216 .dma_max_len = MTK_TX_DMA_BUF_LEN,
217 .dma_len_offset = 16,
218 + .dma_size = MTK_DMA_SIZE(2K),
219 + .fq_dma_size = MTK_DMA_SIZE(2K),
220 },
221 .rx = {
222 .desc_size = sizeof(struct mtk_rx_dma),
223 .irq_done_mask = MTK_RX_DONE_INT,
224 .dma_l4_valid = RX_DMA_L4_VALID,
225 + .dma_size = MTK_DMA_SIZE(2K),
226 .dma_max_len = MTK_TX_DMA_BUF_LEN,
227 .dma_len_offset = 16,
228 },
229 @@ -5027,11 +5046,14 @@ static const struct mtk_soc_data mt7623_
230 .desc_size = sizeof(struct mtk_tx_dma),
231 .dma_max_len = MTK_TX_DMA_BUF_LEN,
232 .dma_len_offset = 16,
233 + .dma_size = MTK_DMA_SIZE(2K),
234 + .fq_dma_size = MTK_DMA_SIZE(2K),
235 },
236 .rx = {
237 .desc_size = sizeof(struct mtk_rx_dma),
238 .irq_done_mask = MTK_RX_DONE_INT,
239 .dma_l4_valid = RX_DMA_L4_VALID,
240 + .dma_size = MTK_DMA_SIZE(2K),
241 .dma_max_len = MTK_TX_DMA_BUF_LEN,
242 .dma_len_offset = 16,
243 },
244 @@ -5050,11 +5072,14 @@ static const struct mtk_soc_data mt7629_
245 .desc_size = sizeof(struct mtk_tx_dma),
246 .dma_max_len = MTK_TX_DMA_BUF_LEN,
247 .dma_len_offset = 16,
248 + .dma_size = MTK_DMA_SIZE(2K),
249 + .fq_dma_size = MTK_DMA_SIZE(2K),
250 },
251 .rx = {
252 .desc_size = sizeof(struct mtk_rx_dma),
253 .irq_done_mask = MTK_RX_DONE_INT,
254 .dma_l4_valid = RX_DMA_L4_VALID,
255 + .dma_size = MTK_DMA_SIZE(2K),
256 .dma_max_len = MTK_TX_DMA_BUF_LEN,
257 .dma_len_offset = 16,
258 },
259 @@ -5076,6 +5101,8 @@ static const struct mtk_soc_data mt7981_
260 .desc_size = sizeof(struct mtk_tx_dma_v2),
261 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
262 .dma_len_offset = 8,
263 + .dma_size = MTK_DMA_SIZE(2K),
264 + .fq_dma_size = MTK_DMA_SIZE(2K),
265 },
266 .rx = {
267 .desc_size = sizeof(struct mtk_rx_dma),
268 @@ -5083,6 +5110,7 @@ static const struct mtk_soc_data mt7981_
269 .dma_l4_valid = RX_DMA_L4_VALID_V2,
270 .dma_max_len = MTK_TX_DMA_BUF_LEN,
271 .dma_len_offset = 16,
272 + .dma_size = MTK_DMA_SIZE(2K),
273 },
274 };
275
276 @@ -5102,6 +5130,8 @@ static const struct mtk_soc_data mt7986_
277 .desc_size = sizeof(struct mtk_tx_dma_v2),
278 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
279 .dma_len_offset = 8,
280 + .dma_size = MTK_DMA_SIZE(2K),
281 + .fq_dma_size = MTK_DMA_SIZE(2K),
282 },
283 .rx = {
284 .desc_size = sizeof(struct mtk_rx_dma),
285 @@ -5109,6 +5139,7 @@ static const struct mtk_soc_data mt7986_
286 .dma_l4_valid = RX_DMA_L4_VALID_V2,
287 .dma_max_len = MTK_TX_DMA_BUF_LEN,
288 .dma_len_offset = 16,
289 + .dma_size = MTK_DMA_SIZE(2K),
290 },
291 };
292
293 @@ -5128,6 +5159,8 @@ static const struct mtk_soc_data mt7988_
294 .desc_size = sizeof(struct mtk_tx_dma_v2),
295 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
296 .dma_len_offset = 8,
297 + .dma_size = MTK_DMA_SIZE(2K),
298 + .fq_dma_size = MTK_DMA_SIZE(4K),
299 },
300 .rx = {
301 .desc_size = sizeof(struct mtk_rx_dma_v2),
302 @@ -5135,6 +5168,7 @@ static const struct mtk_soc_data mt7988_
303 .dma_l4_valid = RX_DMA_L4_VALID_V2,
304 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
305 .dma_len_offset = 8,
306 + .dma_size = MTK_DMA_SIZE(2K),
307 },
308 };
309
310 @@ -5149,6 +5183,7 @@ static const struct mtk_soc_data rt5350_
311 .desc_size = sizeof(struct mtk_tx_dma),
312 .dma_max_len = MTK_TX_DMA_BUF_LEN,
313 .dma_len_offset = 16,
314 + .dma_size = MTK_DMA_SIZE(2K),
315 },
316 .rx = {
317 .desc_size = sizeof(struct mtk_rx_dma),
318 @@ -5156,6 +5191,7 @@ static const struct mtk_soc_data rt5350_
319 .dma_l4_valid = RX_DMA_L4_VALID_PDMA,
320 .dma_max_len = MTK_TX_DMA_BUF_LEN,
321 .dma_len_offset = 16,
322 + .dma_size = MTK_DMA_SIZE(2K),
323 },
324 };
325
326 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
327 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
328 @@ -32,7 +32,9 @@
329 #define MTK_TX_DMA_BUF_LEN 0x3fff
330 #define MTK_TX_DMA_BUF_LEN_V2 0xffff
331 #define MTK_QDMA_RING_SIZE 2048
332 -#define MTK_DMA_SIZE 512
333 +#define MTK_DMA_SIZE(x) (SZ_##x)
334 +#define MTK_FQ_DMA_HEAD 32
335 +#define MTK_FQ_DMA_LENGTH 2048
336 #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + ETH_FCS_LEN)
337 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
338 #define MTK_DMA_DUMMY_DESC 0xffffffff
339 @@ -1173,6 +1175,8 @@ struct mtk_soc_data {
340 u32 desc_size;
341 u32 dma_max_len;
342 u32 dma_len_offset;
343 + u32 dma_size;
344 + u32 fq_dma_size;
345 } tx;
346 struct {
347 u32 desc_size;
348 @@ -1180,6 +1184,7 @@ struct mtk_soc_data {
349 u32 dma_l4_valid;
350 u32 dma_max_len;
351 u32 dma_len_offset;
352 + u32 dma_size;
353 } rx;
354 };
355
356 @@ -1261,7 +1266,7 @@ struct mtk_eth {
357 struct napi_struct rx_napi;
358 void *scratch_ring;
359 dma_addr_t phy_scratch_ring;
360 - void *scratch_head;
361 + void *scratch_head[MTK_FQ_DMA_HEAD];
362 struct clk *clks[MTK_CLK_MAX];
363
364 struct mii_bus *mii_bus;
Staging tree of Piotr Dymacz