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From 82a58061ada60058ec00113c179380f945914709 Mon Sep 17 00:00:00 2001
From: William Zhang <william.zhang@broadcom.com>
Date: Wed, 8 Jun 2022 11:00:59 -0700
Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM63146

Add DTS for ARMv8 based broadband SoC BCM63146. bcm63146.dtsi is the
SoC description DTS header and bcm963146.dts is a simple DTS file for
Broadcom BCM963146 Reference board that only enable the UART port.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/arm64/boot/dts/broadcom/bcmbca/Makefile  |   3 +-
 .../boot/dts/broadcom/bcmbca/bcm63146.dtsi    | 110 ++++++++++++++++++
 .../boot/dts/broadcom/bcmbca/bcm963146.dts    |  30 +++++
 3 files changed, 142 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
 create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts

--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
                                bcm963158.dtb \
-                               bcm96858.dtb
+                               bcm96858.dtb \
+                               bcm963146.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+       compatible = "brcm,bcm63146", "brcm,bcmbca";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       interrupt-parent = <&gic>;
+
+       cpus {
+               #address-cells = <2>;
+               #size-cells = <0>;
+
+               B53_0: cpu@0 {
+                       compatible = "brcm,brahma-b53";
+                       device_type = "cpu";
+                       reg = <0x0 0x0>;
+                       next-level-cache = <&L2_0>;
+                       enable-method = "psci";
+               };
+
+               B53_1: cpu@1 {
+                       compatible = "brcm,brahma-b53";
+                       device_type = "cpu";
+                       reg = <0x0 0x1>;
+                       next-level-cache = <&L2_0>;
+                       enable-method = "psci";
+               };
+
+               L2_0: l2-cache0 {
+                       compatible = "cache";
+               };
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                       <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                       <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                       <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+       };
+
+       pmu: pmu {
+               compatible = "arm,cortex-a53-pmu";
+               interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                       <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&B53_0>, <&B53_1>;
+       };
+
+       clocks: clocks {
+               periph_clk: periph-clk {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <200000000>;
+               };
+               uart_clk: uart-clk {
+                       compatible = "fixed-factor-clock";
+                       #clock-cells = <0>;
+                       clocks = <&periph_clk>;
+                       clock-div = <4>;
+                       clock-mult = <1>;
+               };
+       };
+
+       psci {
+               compatible = "arm,psci-0.2";
+               method = "smc";
+       };
+
+       axi@81000000 {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x0 0x0 0x81000000 0x8000>;
+
+               gic: interrupt-controller@1000 {
+                       compatible = "arm,gic-400";
+                       #interrupt-cells = <3>;
+                       interrupt-controller;
+                       reg = <0x1000 0x1000>,
+                               <0x2000 0x2000>,
+                               <0x4000 0x2000>,
+                               <0x6000 0x2000>;
+                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+                                       IRQ_TYPE_LEVEL_HIGH)>;
+               };
+       };
+
+       bus@ff800000 {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x0 0x0 0xff800000 0x800000>;
+
+               uart0: serial@12000 {
+                       compatible = "arm,pl011", "arm,primecell";
+                       reg = <0x12000 0x1000>;
+                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&uart_clk>, <&uart_clk>;
+                       clock-names = "uartclk", "apb_pclk";
+                       status = "disabled";
+               };
+       };
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm63146.dtsi"
+
+/ {
+       model = "Broadcom BCM963146 Reference Board";
+       compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca";
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x08000000>;
+       };
+};
+
+&uart0 {
+       status = "okay";
+};