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1 From patchwork Mon Dec 27 16:09:22 2021
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3 MIME-Version: 1.0
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5 X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
6 X-Patchwork-Id: 12699860
7 X-Patchwork-Delegate: kuba@kernel.org
8 Date: Mon, 27 Dec 2021 16:09:22 +0000
9 From: Daniel Golle <daniel@makrotopia.org>
10 To: linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
11 linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
12 Cc: Felix Fietkau <nbd@nbd.name>, John Crispin <john@phrozen.org>,
13 Sean Wang <sean.wang@mediatek.com>,
14 Mark Lee <Mark-MC.Lee@mediatek.com>,
15 "David S. Miller" <davem@davemloft.net>,
16 Jakub Kicinski <kuba@kernel.org>,
17 Matthias Brugger <matthias.bgg@gmail.com>,
18 Russell King <linux@armlinux.org.uk>,
19 Andrew Lunn <andrew@lunn.ch>
20 Subject: [PATCH v3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO
21 access
22 Message-ID: <YcnlMtninjjjPhjI@makrotopia.org>
23 References: <YcjsFnbg87o45ltd@lunn.ch>
24 <YcjjzNJ159Bo1xk7@lunn.ch>
25 <YcjlMCacTTJ4RsSA@shell.armlinux.org.uk>
26 <YcjepQ2fmkPZ2+pE@makrotopia.org>
27 MIME-Version: 1.0
28 Content-Disposition: inline
29 In-Reply-To: <YcjsFnbg87o45ltd@lunn.ch>
30 <YcjjzNJ159Bo1xk7@lunn.ch>
31 <YcjlMCacTTJ4RsSA@shell.armlinux.org.uk>
32 <YcjepQ2fmkPZ2+pE@makrotopia.org>
33 Precedence: bulk
34 List-ID: <netdev.vger.kernel.org>
35 X-Mailing-List: netdev@vger.kernel.org
36 X-Patchwork-Delegate: kuba@kernel.org
37
38 Implement read and write access to IEEE 802.3 Clause 45 Ethernet
39 phy registers.
40 Tested on the Ubiquiti UniFi 6 LR access point featuring
41 MediaTek MT7622BV WiSoC with Aquantia AQR112C.
42
43 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
44 ---
45 v3: return -1 instead of 0xffff on error in _mtk_mdio_write
46 v2: use MII_DEVADDR_C45_SHIFT and MII_REGADDR_C45_MASK to extract
47 device id and register address. Unify read and write functions to
48 have identical types and parameter names where possible as we are
49 anyway already replacing both function bodies.
50
51 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 62 +++++++++++++++++----
52 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 +
53 2 files changed, 54 insertions(+), 11 deletions(-)
54
55 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
56 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
57 @@ -95,18 +95,38 @@ static int mtk_mdio_busy_wait(struct mtk
58 return -1;
59 }
60
61 -static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
62 - u32 phy_register, u32 write_data)
63 +static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg,
64 + u32 write_data)
65 {
66 if (mtk_mdio_busy_wait(eth))
67 return -1;
68
69 write_data &= 0xffff;
70
71 - mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
72 - (phy_register << PHY_IAC_REG_SHIFT) |
73 - (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
74 - MTK_PHY_IAC);
75 + if (phy_reg & MII_ADDR_C45) {
76 + u8 dev_num = (phy_reg >> MII_DEVADDR_C45_SHIFT) & GENMASK(4, 0);
77 + u16 reg = (u16)(phy_reg & MII_REGADDR_C45_MASK);
78 +
79 + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_SET_ADDR |
80 + (phy_addr << PHY_IAC_ADDR_SHIFT) |
81 + (dev_num << PHY_IAC_REG_SHIFT) |
82 + reg,
83 + MTK_PHY_IAC);
84 +
85 + if (mtk_mdio_busy_wait(eth))
86 + return -1;
87 +
88 + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_WRITE |
89 + (phy_addr << PHY_IAC_ADDR_SHIFT) |
90 + (dev_num << PHY_IAC_REG_SHIFT) |
91 + write_data,
92 + MTK_PHY_IAC);
93 + } else {
94 + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
95 + (phy_reg << PHY_IAC_REG_SHIFT) |
96 + (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
97 + MTK_PHY_IAC);
98 + }
99
100 if (mtk_mdio_busy_wait(eth))
101 return -1;
102 @@ -114,17 +134,36 @@ static u32 _mtk_mdio_write(struct mtk_et
103 return 0;
104 }
105
106 -static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
107 +static u32 _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg)
108 {
109 u32 d;
110
111 if (mtk_mdio_busy_wait(eth))
112 return 0xffff;
113
114 - mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
115 - (phy_reg << PHY_IAC_REG_SHIFT) |
116 - (phy_addr << PHY_IAC_ADDR_SHIFT),
117 - MTK_PHY_IAC);
118 + if (phy_reg & MII_ADDR_C45) {
119 + u8 dev_num = (phy_reg >> MII_DEVADDR_C45_SHIFT) & GENMASK(4, 0);
120 + u16 reg = (u16)(phy_reg & MII_REGADDR_C45_MASK);
121 +
122 + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_SET_ADDR |
123 + (phy_addr << PHY_IAC_ADDR_SHIFT) |
124 + (dev_num << PHY_IAC_REG_SHIFT) |
125 + reg,
126 + MTK_PHY_IAC);
127 +
128 + if (mtk_mdio_busy_wait(eth))
129 + return 0xffff;
130 +
131 + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_READ_C45 |
132 + (phy_addr << PHY_IAC_ADDR_SHIFT) |
133 + (dev_num << PHY_IAC_REG_SHIFT),
134 + MTK_PHY_IAC);
135 + } else {
136 + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
137 + (phy_reg << PHY_IAC_REG_SHIFT) |
138 + (phy_addr << PHY_IAC_ADDR_SHIFT),
139 + MTK_PHY_IAC);
140 + }
141
142 if (mtk_mdio_busy_wait(eth))
143 return 0xffff;
144 @@ -584,6 +623,7 @@ static int mtk_mdio_init(struct mtk_eth
145 eth->mii_bus->name = "mdio";
146 eth->mii_bus->read = mtk_mdio_read;
147 eth->mii_bus->write = mtk_mdio_write;
148 + eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
149 eth->mii_bus->priv = eth;
150 eth->mii_bus->parent = eth->dev;
151
152 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
153 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
154 @@ -340,9 +340,12 @@
155 /* PHY Indirect Access Control registers */
156 #define MTK_PHY_IAC 0x10004
157 #define PHY_IAC_ACCESS BIT(31)
158 +#define PHY_IAC_SET_ADDR 0
159 #define PHY_IAC_READ BIT(19)
160 +#define PHY_IAC_READ_C45 (BIT(18) | BIT(19))
161 #define PHY_IAC_WRITE BIT(18)
162 #define PHY_IAC_START BIT(16)
163 +#define PHY_IAC_START_C45 0
164 #define PHY_IAC_ADDR_SHIFT 20
165 #define PHY_IAC_REG_SHIFT 25
166 #define PHY_IAC_TIMEOUT HZ
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