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1 From 83fe3df057e641cd0e88425e579d7a5a370ca430 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
3 Date: Mon, 22 Apr 2024 10:15:11 +0300
4 Subject: [PATCH 04/15] net: dsa: mt7530: rename mt753x_bpdu_port_fw enum to
5 mt753x_to_cpu_fw
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 The mt753x_bpdu_port_fw enum is globally used for manipulating the process
11 of deciding the forwardable ports, specifically concerning the CPU port(s).
12 Therefore, rename it and the values in it to mt753x_to_cpu_fw.
13
14 Change FOLLOW_MFC to SYSTEM_DEFAULT to be on par with the switch documents.
15
16 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
17 ---
18 drivers/net/dsa/mt7530.c | 44 ++++++++++-------------
19 drivers/net/dsa/mt7530.h | 76 ++++++++++++++++++++--------------------
20 2 files changed, 56 insertions(+), 64 deletions(-)
21
22 --- a/drivers/net/dsa/mt7530.c
23 +++ b/drivers/net/dsa/mt7530.c
24 @@ -1100,42 +1100,34 @@ mt753x_trap_frames(struct mt7530_priv *p
25 * VLAN-untagged.
26 */
27 mt7530_rmw(priv, MT753X_BPC,
28 - MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK |
29 - MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
30 - MT753X_BPDU_PORT_FW_MASK,
31 - MT753X_PAE_BPDU_FR |
32 - MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
33 - MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
34 - MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
35 - MT753X_BPDU_CPU_ONLY);
36 + PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK |
37 + BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK,
38 + PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
39 + PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) |
40 + BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
41 + TO_CPU_FW_CPU_ONLY);
42
43 /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
44 * them VLAN-untagged.
45 */
46 mt7530_rmw(priv, MT753X_RGAC1,
47 - MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK |
48 - MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR |
49 - MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK,
50 - MT753X_R02_BPDU_FR |
51 - MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
52 - MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
53 - MT753X_R01_BPDU_FR |
54 - MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
55 - MT753X_BPDU_CPU_ONLY);
56 + R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK |
57 + R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK,
58 + R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
59 + R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR |
60 + R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
61 + TO_CPU_FW_CPU_ONLY);
62
63 /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
64 * them VLAN-untagged.
65 */
66 mt7530_rmw(priv, MT753X_RGAC2,
67 - MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK |
68 - MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR |
69 - MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK,
70 - MT753X_R0E_BPDU_FR |
71 - MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
72 - MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
73 - MT753X_R03_BPDU_FR |
74 - MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
75 - MT753X_BPDU_CPU_ONLY);
76 + R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK |
77 + R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK,
78 + R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
79 + R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR |
80 + R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
81 + TO_CPU_FW_CPU_ONLY);
82 }
83
84 static void
85 --- a/drivers/net/dsa/mt7530.h
86 +++ b/drivers/net/dsa/mt7530.h
87 @@ -67,47 +67,47 @@ enum mt753x_id {
88 #define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
89 MT7531_MIRROR_MASK : MIRROR_MASK)
90
91 -/* Registers for BPDU and PAE frame control*/
92 +/* Register for BPDU and PAE frame control */
93 #define MT753X_BPC 0x24
94 -#define MT753X_PAE_BPDU_FR BIT(25)
95 -#define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22)
96 -#define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x)
97 -#define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16)
98 -#define MT753X_PAE_PORT_FW(x) FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x)
99 -#define MT753X_BPDU_EG_TAG_MASK GENMASK(8, 6)
100 -#define MT753X_BPDU_EG_TAG(x) FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x)
101 -#define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
102 +#define PAE_BPDU_FR BIT(25)
103 +#define PAE_EG_TAG_MASK GENMASK(24, 22)
104 +#define PAE_EG_TAG(x) FIELD_PREP(PAE_EG_TAG_MASK, x)
105 +#define PAE_PORT_FW_MASK GENMASK(18, 16)
106 +#define PAE_PORT_FW(x) FIELD_PREP(PAE_PORT_FW_MASK, x)
107 +#define BPDU_EG_TAG_MASK GENMASK(8, 6)
108 +#define BPDU_EG_TAG(x) FIELD_PREP(BPDU_EG_TAG_MASK, x)
109 +#define BPDU_PORT_FW_MASK GENMASK(2, 0)
110
111 -/* Register for :01 and :02 MAC DA frame control */
112 +/* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */
113 #define MT753X_RGAC1 0x28
114 -#define MT753X_R02_BPDU_FR BIT(25)
115 -#define MT753X_R02_EG_TAG_MASK GENMASK(24, 22)
116 -#define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)
117 -#define MT753X_R02_PORT_FW_MASK GENMASK(18, 16)
118 -#define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)
119 -#define MT753X_R01_BPDU_FR BIT(9)
120 -#define MT753X_R01_EG_TAG_MASK GENMASK(8, 6)
121 -#define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)
122 -#define MT753X_R01_PORT_FW_MASK GENMASK(2, 0)
123 +#define R02_BPDU_FR BIT(25)
124 +#define R02_EG_TAG_MASK GENMASK(24, 22)
125 +#define R02_EG_TAG(x) FIELD_PREP(R02_EG_TAG_MASK, x)
126 +#define R02_PORT_FW_MASK GENMASK(18, 16)
127 +#define R02_PORT_FW(x) FIELD_PREP(R02_PORT_FW_MASK, x)
128 +#define R01_BPDU_FR BIT(9)
129 +#define R01_EG_TAG_MASK GENMASK(8, 6)
130 +#define R01_EG_TAG(x) FIELD_PREP(R01_EG_TAG_MASK, x)
131 +#define R01_PORT_FW_MASK GENMASK(2, 0)
132
133 -/* Register for :03 and :0E MAC DA frame control */
134 +/* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */
135 #define MT753X_RGAC2 0x2c
136 -#define MT753X_R0E_BPDU_FR BIT(25)
137 -#define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22)
138 -#define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)
139 -#define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16)
140 -#define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
141 -#define MT753X_R03_BPDU_FR BIT(9)
142 -#define MT753X_R03_EG_TAG_MASK GENMASK(8, 6)
143 -#define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)
144 -#define MT753X_R03_PORT_FW_MASK GENMASK(2, 0)
145 +#define R0E_BPDU_FR BIT(25)
146 +#define R0E_EG_TAG_MASK GENMASK(24, 22)
147 +#define R0E_EG_TAG(x) FIELD_PREP(R0E_EG_TAG_MASK, x)
148 +#define R0E_PORT_FW_MASK GENMASK(18, 16)
149 +#define R0E_PORT_FW(x) FIELD_PREP(R0E_PORT_FW_MASK, x)
150 +#define R03_BPDU_FR BIT(9)
151 +#define R03_EG_TAG_MASK GENMASK(8, 6)
152 +#define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x)
153 +#define R03_PORT_FW_MASK GENMASK(2, 0)
154
155 -enum mt753x_bpdu_port_fw {
156 - MT753X_BPDU_FOLLOW_MFC,
157 - MT753X_BPDU_CPU_EXCLUDE = 4,
158 - MT753X_BPDU_CPU_INCLUDE = 5,
159 - MT753X_BPDU_CPU_ONLY = 6,
160 - MT753X_BPDU_DROP = 7,
161 +enum mt753x_to_cpu_fw {
162 + TO_CPU_FW_SYSTEM_DEFAULT,
163 + TO_CPU_FW_CPU_EXCLUDE = 4,
164 + TO_CPU_FW_CPU_INCLUDE = 5,
165 + TO_CPU_FW_CPU_ONLY = 6,
166 + TO_CPU_FW_DROP = 7,
167 };
168
169 /* Registers for address table access */
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