git.openwrt.org Git - openwrt/staging/nbd.git/blob

   1 From 2c241c25b76d105f798881e1a3c6e3c09c3b27ff Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Mon, 13 Jan 2020 13:40:37 +0100
   4 Subject: [PATCH] drm/vc4: crtc: Add function to compute FIFO level
   5  bits
   6
   7 The longer FIFOs in vc5 pixelvalves means that the FIFO full level
   8 doesn't fit in the original register field and that we also have a
   9 secondary field. In order to prepare for this, let's move the registers
  10 fill part to a helper function.
  11
  12 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  13 ---
  14  drivers/gpu/drm/vc4/vc4_crtc.c | 11 +++++++++--
  15  1 file changed, 9 insertions(+), 2 deletions(-)
  16
  17 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  18 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  19 @@ -277,6 +277,14 @@ static u32 vc4_get_fifo_full_level(struc
  20         }
  21  }
  22
  23 +static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc,
  24 +                                            u32 format)
  25 +{
  26 +       u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
  27 +       return VC4_SET_FIELD(level & 0x3f,
  28 +                            PV_CONTROL_FIFO_LEVEL);
  29 +}
  30 +
  31  /*
  32   * Returns the encoder attached to the CRTC.
  33   *
  34 @@ -377,9 +385,8 @@ static void vc4_crtc_config_pv(struct dr
  35         CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
  36
  37         CRTC_WRITE(PV_CONTROL,
  38 +                  vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
  39                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
  40 -                  VC4_SET_FIELD(vc4_get_fifo_full_level(vc4_crtc, format),
  41 -                                PV_CONTROL_FIFO_LEVEL) |
  42                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
  43                    PV_CONTROL_CLR_AT_START |
  44                    PV_CONTROL_TRIGGER_UNDERFLOW |