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   1 From 9f3a0f34b84ad1b9a8f2bdae44b66f16685b2143 Mon Sep 17 00:00:00 2001
   2 From: Bert Vermeulen <bert@biot.com>
   3 Date: Fri, 22 Jan 2021 21:42:24 +0100
   4 Subject: irqchip: Add support for Realtek RTL838x/RTL839x interrupt controller
   5
   6 This is a standard IRQ driver with only status and mask registers.
   7
   8 The mapping from SoC interrupts (18-31) to MIPS core interrupts is
   9 done via an interrupt-map in device tree.
  10
  11 Signed-off-by: Bert Vermeulen <bert@biot.com>
  12 Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
  13 Acked-by: John Crispin <john@phrozen.org>
  14 Signed-off-by: Marc Zyngier <maz@kernel.org>
  15 Link: https://lore.kernel.org/r/20210122204224.509124-3-bert@biot.com
  16 ---
  17  drivers/irqchip/Makefile          |   1 +
  18  drivers/irqchip/irq-realtek-rtl.c | 180 ++++++++++++++++++++++++++++++++++++++
  19  2 files changed, 181 insertions(+)
  20  create mode 100644 drivers/irqchip/irq-realtek-rtl.c
  21
  22 --- a/drivers/irqchip/Makefile
  23 +++ b/drivers/irqchip/Makefile
  24 @@ -114,3 +114,4 @@ obj-$(CONFIG_LOONGSON_PCH_PIC)              += irq-l
  25  obj-$(CONFIG_LOONGSON_PCH_MSI)         += irq-loongson-pch-msi.o
  26  obj-$(CONFIG_MST_IRQ)                  += irq-mst-intc.o
  27  obj-$(CONFIG_SL28CPLD_INTC)            += irq-sl28cpld.o
  28 +obj-$(CONFIG_MACH_REALTEK_RTL)         += irq-realtek-rtl.o
  29 --- /dev/null
  30 +++ b/drivers/irqchip/irq-realtek-rtl.c
  31 @@ -0,0 +1,180 @@
  32 +// SPDX-License-Identifier: GPL-2.0-only
  33 +/*
  34 + * Copyright (C) 2020 Birger Koblitz <mail@birger-koblitz.de>
  35 + * Copyright (C) 2020 Bert Vermeulen <bert@biot.com>
  36 + * Copyright (C) 2020 John Crispin <john@phrozen.org>
  37 + */
  38 +
  39 +#include <linux/of_irq.h>
  40 +#include <linux/irqchip.h>
  41 +#include <linux/spinlock.h>
  42 +#include <linux/of_address.h>
  43 +#include <linux/irqchip/chained_irq.h>
  44 +
  45 +/* Global Interrupt Mask Register */
  46 +#define RTL_ICTL_GIMR          0x00
  47 +/* Global Interrupt Status Register */
  48 +#define RTL_ICTL_GISR          0x04
  49 +/* Interrupt Routing Registers */
  50 +#define RTL_ICTL_IRR0          0x08
  51 +#define RTL_ICTL_IRR1          0x0c
  52 +#define RTL_ICTL_IRR2          0x10
  53 +#define RTL_ICTL_IRR3          0x14
  54 +
  55 +#define REG(x)         (realtek_ictl_base + x)
  56 +
  57 +static DEFINE_RAW_SPINLOCK(irq_lock);
  58 +static void __iomem *realtek_ictl_base;
  59 +
  60 +static void realtek_ictl_unmask_irq(struct irq_data *i)
  61 +{
  62 +       unsigned long flags;
  63 +       u32 value;
  64 +
  65 +       raw_spin_lock_irqsave(&irq_lock, flags);
  66 +
  67 +       value = readl(REG(RTL_ICTL_GIMR));
  68 +       value |= BIT(i->hwirq);
  69 +       writel(value, REG(RTL_ICTL_GIMR));
  70 +
  71 +       raw_spin_unlock_irqrestore(&irq_lock, flags);
  72 +}
  73 +
  74 +static void realtek_ictl_mask_irq(struct irq_data *i)
  75 +{
  76 +       unsigned long flags;
  77 +       u32 value;
  78 +
  79 +       raw_spin_lock_irqsave(&irq_lock, flags);
  80 +
  81 +       value = readl(REG(RTL_ICTL_GIMR));
  82 +       value &= ~BIT(i->hwirq);
  83 +       writel(value, REG(RTL_ICTL_GIMR));
  84 +
  85 +       raw_spin_unlock_irqrestore(&irq_lock, flags);
  86 +}
  87 +
  88 +static struct irq_chip realtek_ictl_irq = {
  89 +       .name = "realtek-rtl-intc",
  90 +       .irq_mask = realtek_ictl_mask_irq,
  91 +       .irq_unmask = realtek_ictl_unmask_irq,
  92 +};
  93 +
  94 +static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
  95 +{
  96 +       irq_set_chip_and_handler(hw, &realtek_ictl_irq, handle_level_irq);
  97 +
  98 +       return 0;
  99 +}
 100 +
 101 +static const struct irq_domain_ops irq_domain_ops = {
 102 +       .map = intc_map,
 103 +       .xlate = irq_domain_xlate_onecell,
 104 +};
 105 +
 106 +static void realtek_irq_dispatch(struct irq_desc *desc)
 107 +{
 108 +       struct irq_chip *chip = irq_desc_get_chip(desc);
 109 +       struct irq_domain *domain;
 110 +       unsigned int pending;
 111 +
 112 +       chained_irq_enter(chip, desc);
 113 +       pending = readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR));
 114 +       if (unlikely(!pending)) {
 115 +               spurious_interrupt();
 116 +               goto out;
 117 +       }
 118 +       domain = irq_desc_get_handler_data(desc);
 119 +       generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
 120 +
 121 +out:
 122 +       chained_irq_exit(chip, desc);
 123 +}
 124 +
 125 +/*
 126 + * SoC interrupts are cascaded to MIPS CPU interrupts according to the
 127 + * interrupt-map in the device tree. Each SoC interrupt gets 4 bits for
 128 + * the CPU interrupt in an Interrupt Routing Register. Max 32 SoC interrupts
 129 + * thus go into 4 IRRs.
 130 + */
 131 +static int __init map_interrupts(struct device_node *node, struct irq_domain *domain)
 132 +{
 133 +       struct device_node *cpu_ictl;
 134 +       const __be32 *imap;
 135 +       u32 imaplen, soc_int, cpu_int, tmp, regs[4];
 136 +       int ret, i, irr_regs[] = {
 137 +               RTL_ICTL_IRR3,
 138 +               RTL_ICTL_IRR2,
 139 +               RTL_ICTL_IRR1,
 140 +               RTL_ICTL_IRR0,
 141 +       };
 142 +       u8 mips_irqs_set;
 143 +
 144 +       ret = of_property_read_u32(node, "#address-cells", &tmp);
 145 +       if (ret || tmp)
 146 +               return -EINVAL;
 147 +
 148 +       imap = of_get_property(node, "interrupt-map", &imaplen);
 149 +       if (!imap || imaplen % 3)
 150 +               return -EINVAL;
 151 +
 152 +       mips_irqs_set = 0;
 153 +       memset(regs, 0, sizeof(regs));
 154 +       for (i = 0; i < imaplen; i += 3 * sizeof(u32)) {
 155 +               soc_int = be32_to_cpup(imap);
 156 +               if (soc_int > 31)
 157 +                       return -EINVAL;
 158 +
 159 +               cpu_ictl = of_find_node_by_phandle(be32_to_cpup(imap + 1));
 160 +               if (!cpu_ictl)
 161 +                       return -EINVAL;
 162 +               ret = of_property_read_u32(cpu_ictl, "#interrupt-cells", &tmp);
 163 +               if (ret || tmp != 1)
 164 +                       return -EINVAL;
 165 +               of_node_put(cpu_ictl);
 166 +
 167 +               cpu_int = be32_to_cpup(imap + 2);
 168 +               if (cpu_int > 7)
 169 +                       return -EINVAL;
 170 +
 171 +               if (!(mips_irqs_set & BIT(cpu_int))) {
 172 +                       irq_set_chained_handler_and_data(cpu_int, realtek_irq_dispatch,
 173 +                                                        domain);
 174 +                       mips_irqs_set |= BIT(cpu_int);
 175 +               }
 176 +
 177 +               regs[(soc_int * 4) / 32] |= cpu_int << (soc_int * 4) % 32;
 178 +               imap += 3;
 179 +       }
 180 +
 181 +       for (i = 0; i < 4; i++)
 182 +               writel(regs[i], REG(irr_regs[i]));
 183 +
 184 +       return 0;
 185 +}
 186 +
 187 +static int __init realtek_rtl_of_init(struct device_node *node, struct device_node *parent)
 188 +{
 189 +       struct irq_domain *domain;
 190 +       int ret;
 191 +
 192 +       realtek_ictl_base = of_iomap(node, 0);
 193 +       if (!realtek_ictl_base)
 194 +               return -ENXIO;
 195 +
 196 +       /* Disable all cascaded interrupts */
 197 +       writel(0, REG(RTL_ICTL_GIMR));
 198 +
 199 +       domain = irq_domain_add_simple(node, 32, 0,
 200 +                                      &irq_domain_ops, NULL);
 201 +
 202 +       ret = map_interrupts(node, domain);
 203 +       if (ret) {
 204 +               pr_err("invalid interrupt map\n");
 205 +               return ret;
 206 +       }
 207 +
 208 +       return 0;
 209 +}
 210 +
 211 +IRQCHIP_DECLARE(realtek_rtl_intc, "realtek,rtl-intc", realtek_rtl_of_init);