git.openwrt.org Git - openwrt/staging/ynezz.git/blob

   1 From 6960d2c4f5e95ae304a62af249d6c92a2d952601 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Manoil <claudiu.manoil@nxp.com>
   3 Date: Thu, 14 Nov 2019 17:03:21 +0200
   4 Subject: [PATCH] net: mscc: ocelot: filter out ocelot SoC specific PCS config
   5  from common path
   6
   7 The adjust_link routine should be generic enough to be (re)used by
   8 any SoC that integrates a switch core compatible with the Ocelot
   9 core switch driver.  Currently all configurations are generic except
  10 for the PCS settings that are SoC specific.  Move these out to the
  11 Ocelot SoC/board instance.
  12
  13 Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
  14 Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
  15 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  16 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
  17 Signed-off-by: David S. Miller <davem@davemloft.net>
  18 ---
  19  drivers/net/ethernet/mscc/ocelot.c       | 19 ++-----------------
  20  drivers/net/ethernet/mscc/ocelot.h       |  8 +++++++-
  21  drivers/net/ethernet/mscc/ocelot_board.c | 29 ++++++++++++++++++++++++++++-
  22  drivers/net/ethernet/mscc/ocelot_regs.c  |  3 ++-
  23  4 files changed, 39 insertions(+), 20 deletions(-)
  24
  25 --- a/drivers/net/ethernet/mscc/ocelot.c
  26 +++ b/drivers/net/ethernet/mscc/ocelot.c
  27 @@ -455,23 +455,8 @@ static void ocelot_adjust_link(struct oc
  28         ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
  29                            DEV_MAC_HDX_CFG);
  30
  31 -       /* Disable HDX fast control */
  32 -       ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS,
  33 -                          DEV_PORT_MISC);
  34 -
  35 -       /* SGMII only for now */
  36 -       ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA,
  37 -                          PCS1G_MODE_CFG);
  38 -       ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
  39 -
  40 -       /* Enable PCS */
  41 -       ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
  42 -
  43 -       /* No aneg on SGMII */
  44 -       ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG);
  45 -
  46 -       /* No loopback */
  47 -       ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG);
  48 +       if (ocelot->ops->pcs_init)
  49 +               ocelot->ops->pcs_init(ocelot, port);
  50
  51         /* Set Max Length and maximum tags allowed */
  52         ocelot_port_writel(ocelot_port, VLAN_ETH_FRAME_LEN,
  53 --- a/drivers/net/ethernet/mscc/ocelot.h
  54 +++ b/drivers/net/ethernet/mscc/ocelot.h
  55 @@ -435,13 +435,19 @@ enum ocelot_tag_prefix {
  56  };
  57
  58  struct ocelot_port;
  59 +struct ocelot;
  60
  61  struct ocelot_stat_layout {
  62         u32 offset;
  63         char name[ETH_GSTRING_LEN];
  64  };
  65
  66 +struct ocelot_ops {
  67 +       void (*pcs_init)(struct ocelot *ocelot, int port);
  68 +};
  69 +
  70  struct ocelot {
  71 +       const struct ocelot_ops *ops;
  72         struct device *dev;
  73
  74         struct regmap *targets[TARGET_MAX];
  75 @@ -553,7 +559,7 @@ struct regmap *ocelot_regmap_init(struct
  76
  77  int ocelot_init(struct ocelot *ocelot);
  78  void ocelot_deinit(struct ocelot *ocelot);
  79 -int ocelot_chip_init(struct ocelot *ocelot);
  80 +int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops);
  81  int ocelot_probe_port(struct ocelot *ocelot, u8 port,
  82                       void __iomem *regs,
  83                       struct phy_device *phy);
  84 --- a/drivers/net/ethernet/mscc/ocelot_board.c
  85 +++ b/drivers/net/ethernet/mscc/ocelot_board.c
  86 @@ -262,6 +262,33 @@ static const struct of_device_id mscc_oc
  87  };
  88  MODULE_DEVICE_TABLE(of, mscc_ocelot_match);
  89
  90 +static void ocelot_port_pcs_init(struct ocelot *ocelot, int port)
  91 +{
  92 +       struct ocelot_port *ocelot_port = ocelot->ports[port];
  93 +
  94 +       /* Disable HDX fast control */
  95 +       ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS,
  96 +                          DEV_PORT_MISC);
  97 +
  98 +       /* SGMII only for now */
  99 +       ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA,
 100 +                          PCS1G_MODE_CFG);
 101 +       ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
 102 +
 103 +       /* Enable PCS */
 104 +       ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
 105 +
 106 +       /* No aneg on SGMII */
 107 +       ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG);
 108 +
 109 +       /* No loopback */
 110 +       ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG);
 111 +}
 112 +
 113 +static const struct ocelot_ops ocelot_ops = {
 114 +       .pcs_init               = ocelot_port_pcs_init,
 115 +};
 116 +
 117  static int mscc_ocelot_probe(struct platform_device *pdev)
 118  {
 119         struct device_node *np = pdev->dev.of_node;
 120 @@ -323,7 +350,7 @@ static int mscc_ocelot_probe(struct plat
 121
 122         ocelot->targets[HSIO] = hsio;
 123
 124 -       err = ocelot_chip_init(ocelot);
 125 +       err = ocelot_chip_init(ocelot, &ocelot_ops);
 126         if (err)
 127                 return err;
 128
 129 --- a/drivers/net/ethernet/mscc/ocelot_regs.c
 130 +++ b/drivers/net/ethernet/mscc/ocelot_regs.c
 131 @@ -423,7 +423,7 @@ static void ocelot_pll5_init(struct ocel
 132                      HSIO_PLL5G_CFG2_AMPC_SEL(0x10));
 133  }
 134
 135 -int ocelot_chip_init(struct ocelot *ocelot)
 136 +int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops)
 137  {
 138         int ret;
 139
 140 @@ -431,6 +431,7 @@ int ocelot_chip_init(struct ocelot *ocel
 141         ocelot->stats_layout = ocelot_stats_layout;
 142         ocelot->num_stats = ARRAY_SIZE(ocelot_stats_layout);
 143         ocelot->shared_queue_sz = 224 * 1024;
 144 +       ocelot->ops = ops;
 145
 146         ret = ocelot_regfields_init(ocelot, ocelot_regfields);
 147         if (ret)