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1 From dc12953941ed3b8bc9eb8d47f8c7e74f54b47049 Mon Sep 17 00:00:00 2001
2 From: Md Sadre Alam <quic_mdalam@quicinc.com>
3 Date: Mon, 19 Aug 2024 11:05:18 +0530
4 Subject: [PATCH v10 6/8] spi: spi-qpic: add driver for QCOM SPI NAND flash
5 Interface
6
7 This driver implements support for the SPI-NAND mode of QCOM NAND Flash
8 Interface as a SPI-MEM controller with pipelined ECC capability.
9
10 Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
11 Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
12 Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
13 Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
14 Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
15 ---
16
17 Change in [v10]
18
19 * Fixed compilation warnings reported by kernel test robot.
20 * Added depends on CONFIG_MTD
21 * removed extra bracket from statement if (i == (num_cw - 1)) in
22 qcom_spi_program_raw() api.
23
24 Change in [v9]
25
26 * Changed data type of addr1, addr2, cmd, to __le32 in qpic_spi_nand
27 structure
28 * In qcom_spi_set_read_loc_first() api added cpu_to_le32() macro to fix
29 compilation warning
30 * In qcom_spi_set_read_loc_last() api added cpu_to_le32() macro to fix
31 compilation warning
32 * In qcom_spi_init() api added cpu_to_le32() macro to fix compilation
33 warning
34 * In qcom_spi_ecc_init_ctx_pipelined() api removed unused variables
35 reqs, user, step_size, strength and added cpu_to_le32() macro as well
36 to fix compilation warning
37 * In qcom_spi_read_last_cw() api added cpu_to_le32() macro to fix compilation
38 warning
39 * In qcom_spi_check_error() api added cpu_to_le32() macro to fix compilation
40 warning
41 * In qcom_spi_read_page_ecc() api added cpu_to_le32() macro to fix compilation
42 warning
43 * In qcom_spi_read_page_oob() api added cpu_to_le32() macro to fix compilation
44 warning
45 * In qcom_spi_program_raw() api added cpu_to_le32() macro to fix compilation
46 warning
47 * In qcom_spi_program_ecc() api added cpu_to_le32() macro to fix compilation
48 warning
49 * In qcom_spi_program_oob() api added cpu_to_le32() macro to fix compilation
50 warning
51 * In qcom_spi_send_cmdaddr() api added cpu_to_le32() macro to fix compilation
52 warning
53 * In qcom_spi_io_op() api added cpu_to_le32() macro to fix compilation
54 warning
55
56 Change in [v8]
57
58 * Included "bitfield.h" file to /spi-qpic-snand.c
59 to fix compilation warning reported by kernel test robot
60 * Removed unused variable "steps" in
61 qcom_spi_ecc_init_ctx_pipelined() to fix compilation warning
62
63 Change in [v7]
64
65 * Added read_oob() and write_oob() api
66
67 * Handled offset value for oob layout
68
69 * Made CONFIG_SPI_QPIC_SNAND as bool
70
71 * Added macro ecceng_to_qspi()
72
73 * Added FIELD_PREP() Macro in spi init
74
75 * Added else condition in
76 qcom_spi_ecc_finish_io_req_pipelined()
77 for corrected ecc
78
79 * Handled multiple error condition for api
80 qcom_spi_cmd_mapping()
81
82 * Fix typo for printing debug message
83
84 Change in [v6]
85
86 * Added separate qpic_spi_nand{...} struct
87
88 * moved qpic_ecc and qcom_ecc_stats struct to
89 spi-qpic-snand.c file, since its spi nand
90 specific
91
92 * Added FIELD_PREP() and GENMASK() macro
93
94 * Removed rawnand.h and partition.h from
95 spi-qpic-snand.c
96
97 * Removed oob_buff assignment form
98 qcom_spi_write_page_cache
99
100 * Added qcom_nand_unalloc() in remove() path
101
102 * Fixes all all comments
103
104 Change in [v5]
105
106 * Added raw_read() and raw_write() api
107
108 * Updated commit message
109
110 * Removed register indirection
111
112 * Added qcom_spi_ prefix to all the api
113
114 * Removed snand_set_reg() api.
115
116 * Fixed nandbiterr issue
117
118 * Removed hardcoded num_cw and made it variable
119
120 * Removed hardcoded value for mtd pagesize
121
122 * Added -ENOSUPPORT in cmd mapping for unsupported
123 commands
124
125 * Replace if..else with switch..case statement
126
127 Change in [v4]
128
129 * No change
130
131 Change in [v3]
132
133 * Set SPI_QPIC_SNAND to n and added COMPILE_TEST in Kconfig
134
135 * Made driver name sorted in Make file
136
137 * Made comment like c++
138
139 * Changed macro to functions, snandc_set_read_loc_last()
140 and snandc_set_read_loc_first()
141
142 * Added error handling in snandc_set_reg()
143
144 * Changed into normal conditional statement for
145 return snandc->ecc_stats.failed ? -EBADMSG :
146 snandc->ecc_stats.bitflips;
147
148 * Remove cast of wbuf in qpic_snand_program_execute()
149 function
150
151 * Made num_cw variable instead hardcoded value
152
153 * changed if..else condition of function qpic_snand_io_op()
154 to switch..case statement
155
156 * Added __devm_spi_alloc_controller() api instead of
157 devm_spi_alloc_master()
158
159 * Disabling clock in remove path
160
161 Change in [v2]
162
163 * Added initial support for SPI-NAND driver
164
165 Change in [v1]
166
167 * Added RFC patch for design review
168
169 drivers/mtd/nand/Makefile | 5 +-
170 drivers/spi/Kconfig | 9 +
171 drivers/spi/Makefile | 1 +
172 drivers/spi/spi-qpic-snand.c | 1634 ++++++++++++++++++++++++++
173 include/linux/mtd/nand-qpic-common.h | 7 +
174 5 files changed, 1655 insertions(+), 1 deletion(-)
175 create mode 100644 drivers/spi/spi-qpic-snand.c
176
177 --- a/drivers/mtd/nand/Makefile
178 +++ b/drivers/mtd/nand/Makefile
179 @@ -7,8 +7,11 @@ obj-$(CONFIG_MTD_NAND_MTK_BMT) += mtk_bm
180
181 ifeq ($(CONFIG_MTD_NAND_QCOM),y)
182 obj-y += qpic_common.o
183 +else
184 +ifeq ($(CONFIG_SPI_QPIC_SNAND),y)
185 +obj-y += qpic_common.o
186 +endif
187 endif
188 -
189 obj-y += onenand/
190 obj-y += raw/
191 obj-y += spi/
192 --- a/drivers/spi/Kconfig
193 +++ b/drivers/spi/Kconfig
194 @@ -870,6 +870,15 @@ config SPI_QCOM_QSPI
195 help
196 QSPI(Quad SPI) driver for Qualcomm QSPI controller.
197
198 +config SPI_QPIC_SNAND
199 + bool "QPIC SNAND controller"
200 + depends on ARCH_QCOM || COMPILE_TEST
201 + depends on MTD
202 + help
203 + QPIC_SNAND (QPIC SPI NAND) driver for Qualcomm QPIC controller.
204 + QPIC controller supports both parallel nand and serial nand.
205 + This config will enable serial nand driver for QPIC controller.
206 +
207 config SPI_QUP
208 tristate "Qualcomm SPI controller with QUP interface"
209 depends on ARCH_QCOM || COMPILE_TEST
210 --- a/drivers/spi/Makefile
211 +++ b/drivers/spi/Makefile
212 @@ -110,6 +110,7 @@ obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-
213 obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
214 obj-$(CONFIG_SPI_QCOM_GENI) += spi-geni-qcom.o
215 obj-$(CONFIG_SPI_QCOM_QSPI) += spi-qcom-qspi.o
216 +obj-$(CONFIG_SPI_QPIC_SNAND) += spi-qpic-snand.o
217 obj-$(CONFIG_SPI_QUP) += spi-qup.o
218 obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
219 obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o
220 --- /dev/null
221 +++ b/drivers/spi/spi-qpic-snand.c
222 @@ -0,0 +1,1634 @@
223 +/*
224 + * SPDX-License-Identifier: GPL-2.0
225 + *
226 + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
227 + *
228 + * Authors:
229 + * Md Sadre Alam <quic_mdalam@quicinc.com>
230 + * Sricharan R <quic_srichara@quicinc.com>
231 + * Varadarajan Narayanan <quic_varada@quicinc.com>
232 + */
233 +#include <linux/bitops.h>
234 +#include <linux/clk.h>
235 +#include <linux/delay.h>
236 +#include <linux/dmaengine.h>
237 +#include <linux/dma-mapping.h>
238 +#include <linux/dma/qcom_adm.h>
239 +#include <linux/dma/qcom_bam_dma.h>
240 +#include <linux/module.h>
241 +#include <linux/of.h>
242 +#include <linux/platform_device.h>
243 +#include <linux/slab.h>
244 +#include <linux/mtd/nand-qpic-common.h>
245 +#include <linux/mtd/spinand.h>
246 +#include <linux/bitfield.h>
247 +
248 +#define NAND_FLASH_SPI_CFG 0xc0
249 +#define NAND_NUM_ADDR_CYCLES 0xc4
250 +#define NAND_BUSY_CHECK_WAIT_CNT 0xc8
251 +#define NAND_FLASH_FEATURES 0xf64
252 +
253 +/* QSPI NAND config reg bits */
254 +#define LOAD_CLK_CNTR_INIT_EN BIT(28)
255 +#define CLK_CNTR_INIT_VAL_VEC 0x924
256 +#define CLK_CNTR_INIT_VAL_VEC_MASK GENMASK(27, 16)
257 +#define FEA_STATUS_DEV_ADDR 0xc0
258 +#define FEA_STATUS_DEV_ADDR_MASK GENMASK(15, 8)
259 +#define SPI_CFG BIT(0)
260 +#define SPI_NUM_ADDR 0xDA4DB
261 +#define SPI_WAIT_CNT 0x10
262 +#define QPIC_QSPI_NUM_CS 1
263 +#define SPI_TRANSFER_MODE_x1 BIT(29)
264 +#define SPI_TRANSFER_MODE_x4 (3 << 29)
265 +#define SPI_WP BIT(28)
266 +#define SPI_HOLD BIT(27)
267 +#define QPIC_SET_FEATURE BIT(31)
268 +
269 +#define SPINAND_RESET 0xff
270 +#define SPINAND_READID 0x9f
271 +#define SPINAND_GET_FEATURE 0x0f
272 +#define SPINAND_SET_FEATURE 0x1f
273 +#define SPINAND_READ 0x13
274 +#define SPINAND_ERASE 0xd8
275 +#define SPINAND_WRITE_EN 0x06
276 +#define SPINAND_PROGRAM_EXECUTE 0x10
277 +#define SPINAND_PROGRAM_LOAD 0x84
278 +
279 +#define ACC_FEATURE 0xe
280 +#define BAD_BLOCK_MARKER_SIZE 0x2
281 +#define OOB_BUF_SIZE 128
282 +#define ecceng_to_qspi(eng) container_of(eng, struct qpic_spi_nand, ecc_eng)
283 +struct qpic_snand_op {
284 + u32 cmd_reg;
285 + u32 addr1_reg;
286 + u32 addr2_reg;
287 +};
288 +
289 +struct snandc_read_status {
290 + __le32 snandc_flash;
291 + __le32 snandc_buffer;
292 + __le32 snandc_erased_cw;
293 +};
294 +
295 +/*
296 + * ECC state struct
297 + * @corrected: ECC corrected
298 + * @bitflips: Max bit flip
299 + * @failed: ECC failed
300 + */
301 +struct qcom_ecc_stats {
302 + u32 corrected;
303 + u32 bitflips;
304 + u32 failed;
305 +};
306 +
307 +struct qpic_ecc {
308 + struct device *dev;
309 + int ecc_bytes_hw;
310 + int spare_bytes;
311 + int bbm_size;
312 + int ecc_mode;
313 + int bytes;
314 + int steps;
315 + int step_size;
316 + int strength;
317 + int cw_size;
318 + int cw_data;
319 + u32 cfg0;
320 + u32 cfg1;
321 + u32 cfg0_raw;
322 + u32 cfg1_raw;
323 + u32 ecc_buf_cfg;
324 + u32 ecc_bch_cfg;
325 + u32 clrflashstatus;
326 + u32 clrreadstatus;
327 + bool bch_enabled;
328 +};
329 +
330 +struct qpic_spi_nand {
331 + struct qcom_nand_controller *snandc;
332 + struct spi_controller *ctlr;
333 + struct mtd_info *mtd;
334 + struct clk *iomacro_clk;
335 + struct qpic_ecc *ecc;
336 + struct qcom_ecc_stats ecc_stats;
337 + struct nand_ecc_engine ecc_eng;
338 + u8 *data_buf;
339 + u8 *oob_buf;
340 + u32 wlen;
341 + __le32 addr1;
342 + __le32 addr2;
343 + __le32 cmd;
344 + u32 num_cw;
345 + bool oob_rw;
346 + bool page_rw;
347 + bool raw_rw;
348 +};
349 +
350 +static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snandc,
351 + int reg, int cw_offset, int read_size,
352 + int is_last_read_loc)
353 +{
354 + __le32 locreg_val;
355 + u32 val = (((cw_offset) << READ_LOCATION_OFFSET) |
356 + ((read_size) << READ_LOCATION_SIZE) | ((is_last_read_loc)
357 + << READ_LOCATION_LAST));
358 +
359 + locreg_val = cpu_to_le32(val);
360 +
361 + if (reg == NAND_READ_LOCATION_0)
362 + snandc->regs->read_location0 = locreg_val;
363 + else if (reg == NAND_READ_LOCATION_1)
364 + snandc->regs->read_location1 = locreg_val;
365 + else if (reg == NAND_READ_LOCATION_2)
366 + snandc->regs->read_location1 = locreg_val;
367 + else if (reg == NAND_READ_LOCATION_3)
368 + snandc->regs->read_location3 = locreg_val;
369 +}
370 +
371 +static void qcom_spi_set_read_loc_last(struct qcom_nand_controller *snandc,
372 + int reg, int cw_offset, int read_size,
373 + int is_last_read_loc)
374 +{
375 + __le32 locreg_val;
376 + u32 val = (((cw_offset) << READ_LOCATION_OFFSET) |
377 + ((read_size) << READ_LOCATION_SIZE) | ((is_last_read_loc)
378 + << READ_LOCATION_LAST));
379 +
380 + locreg_val = cpu_to_le32(val);
381 +
382 + if (reg == NAND_READ_LOCATION_LAST_CW_0)
383 + snandc->regs->read_location_last0 = locreg_val;
384 + else if (reg == NAND_READ_LOCATION_LAST_CW_1)
385 + snandc->regs->read_location_last1 = locreg_val;
386 + else if (reg == NAND_READ_LOCATION_LAST_CW_2)
387 + snandc->regs->read_location_last2 = locreg_val;
388 + else if (reg == NAND_READ_LOCATION_LAST_CW_3)
389 + snandc->regs->read_location_last3 = locreg_val;
390 +}
391 +
392 +static struct qcom_nand_controller *nand_to_qcom_snand(struct nand_device *nand)
393 +{
394 + struct nand_ecc_engine *eng = nand->ecc.engine;
395 + struct qpic_spi_nand *qspi = ecceng_to_qspi(eng);
396 +
397 + return qspi->snandc;
398 +}
399 +
400 +static int qcom_spi_init(struct qcom_nand_controller *snandc)
401 +{
402 + u32 snand_cfg_val = 0x0;
403 + int ret;
404 +
405 + snand_cfg_val = FIELD_PREP(CLK_CNTR_INIT_VAL_VEC_MASK, CLK_CNTR_INIT_VAL_VEC) |
406 + FIELD_PREP(LOAD_CLK_CNTR_INIT_EN, 0) |
407 + FIELD_PREP(FEA_STATUS_DEV_ADDR_MASK, FEA_STATUS_DEV_ADDR) |
408 + FIELD_PREP(SPI_CFG, 0);
409 +
410 + snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
411 + snandc->regs->num_addr_cycle = cpu_to_le32(SPI_NUM_ADDR);
412 + snandc->regs->busy_wait_cnt = cpu_to_le32(SPI_WAIT_CNT);
413 +
414 + qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
415 +
416 + snand_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN;
417 + snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
418 +
419 + qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
420 +
421 + qcom_write_reg_dma(snandc, &snandc->regs->num_addr_cycle, NAND_NUM_ADDR_CYCLES, 1, 0);
422 + qcom_write_reg_dma(snandc, &snandc->regs->busy_wait_cnt, NAND_BUSY_CHECK_WAIT_CNT, 1,
423 + NAND_BAM_NEXT_SGL);
424 +
425 + ret = qcom_submit_descs(snandc);
426 + if (ret) {
427 + dev_err(snandc->dev, "failure in submitting spi init descriptor\n");
428 + return ret;
429 + }
430 +
431 + return ret;
432 +}
433 +
434 +static int qcom_spi_ooblayout_ecc(struct mtd_info *mtd, int section,
435 + struct mtd_oob_region *oobregion)
436 +{
437 + struct nand_device *nand = mtd_to_nanddev(mtd);
438 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
439 + struct qpic_ecc *qecc = snandc->qspi->ecc;
440 +
441 + if (section > 1)
442 + return -ERANGE;
443 +
444 + oobregion->length = qecc->ecc_bytes_hw + qecc->spare_bytes;
445 + oobregion->offset = mtd->oobsize - oobregion->length;
446 +
447 + return 0;
448 +}
449 +
450 +static int qcom_spi_ooblayout_free(struct mtd_info *mtd, int section,
451 + struct mtd_oob_region *oobregion)
452 +{
453 + struct nand_device *nand = mtd_to_nanddev(mtd);
454 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
455 + struct qpic_ecc *qecc = snandc->qspi->ecc;
456 +
457 + if (section)
458 + return -ERANGE;
459 +
460 + oobregion->length = qecc->steps * 4;
461 + oobregion->offset = ((qecc->steps - 1) * qecc->bytes) + qecc->bbm_size;
462 +
463 + return 0;
464 +}
465 +
466 +static const struct mtd_ooblayout_ops qcom_spi_ooblayout = {
467 + .ecc = qcom_spi_ooblayout_ecc,
468 + .free = qcom_spi_ooblayout_free,
469 +};
470 +
471 +static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand)
472 +{
473 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
474 + struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
475 + struct mtd_info *mtd = nanddev_to_mtd(nand);
476 + int cwperpage, bad_block_byte;
477 + struct qpic_ecc *ecc_cfg;
478 +
479 + cwperpage = mtd->writesize / NANDC_STEP_SIZE;
480 + snandc->qspi->num_cw = cwperpage;
481 +
482 + ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL);
483 + if (!ecc_cfg)
484 + return -ENOMEM;
485 + snandc->qspi->oob_buf = kzalloc(mtd->writesize + mtd->oobsize,
486 + GFP_KERNEL);
487 + if (!snandc->qspi->oob_buf)
488 + return -ENOMEM;
489 +
490 + memset(snandc->qspi->oob_buf, 0xff, mtd->writesize + mtd->oobsize);
491 +
492 + nand->ecc.ctx.priv = ecc_cfg;
493 + snandc->qspi->mtd = mtd;
494 +
495 + ecc_cfg->ecc_bytes_hw = 7;
496 + ecc_cfg->spare_bytes = 4;
497 + ecc_cfg->bbm_size = 1;
498 + ecc_cfg->bch_enabled = true;
499 + ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size;
500 +
501 + ecc_cfg->steps = 4;
502 + ecc_cfg->strength = 4;
503 + ecc_cfg->step_size = 512;
504 + ecc_cfg->cw_data = 516;
505 + ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes;
506 + bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1;
507 +
508 + mtd_set_ooblayout(mtd, &qcom_spi_ooblayout);
509 +
510 + ecc_cfg->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
511 + FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_data) |
512 + FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 1) |
513 + FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
514 + FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, ecc_cfg->ecc_bytes_hw) |
515 + FIELD_PREP(STATUS_BFR_READ, 0) |
516 + FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) |
517 + FIELD_PREP(SPARE_SIZE_BYTES_MASK, ecc_cfg->spare_bytes);
518 +
519 + ecc_cfg->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
520 + FIELD_PREP(CS_ACTIVE_BSY, 0) |
521 + FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) |
522 + FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) |
523 + FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
524 + FIELD_PREP(WIDE_FLASH, 0) |
525 + FIELD_PREP(ENABLE_BCH_ECC, ecc_cfg->bch_enabled);
526 +
527 + ecc_cfg->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
528 + FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
529 + FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_size) |
530 + FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
531 +
532 + ecc_cfg->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
533 + FIELD_PREP(CS_ACTIVE_BSY, 0) |
534 + FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
535 + FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
536 + FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
537 + FIELD_PREP(WIDE_FLASH, 0) |
538 + FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
539 +
540 + ecc_cfg->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !ecc_cfg->bch_enabled) |
541 + FIELD_PREP(ECC_SW_RESET, 0) |
542 + FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) |
543 + FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
544 + FIELD_PREP(ECC_MODE_MASK, 0) |
545 + FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw);
546 +
547 + ecc_cfg->ecc_buf_cfg = 0x203 << NUM_STEPS;
548 + ecc_cfg->clrflashstatus = FS_READY_BSY_N;
549 + ecc_cfg->clrreadstatus = 0xc0;
550 +
551 + conf->step_size = ecc_cfg->step_size;
552 + conf->strength = ecc_cfg->strength;
553 +
554 + snandc->regs->erased_cw_detect_cfg_clr = cpu_to_le32(CLR_ERASED_PAGE_DET);
555 + snandc->regs->erased_cw_detect_cfg_set = cpu_to_le32(SET_ERASED_PAGE_DET);
556 +
557 + dev_dbg(snandc->dev, "ECC strength: %u bits per %u bytes\n",
558 + ecc_cfg->strength, ecc_cfg->step_size);
559 +
560 + return 0;
561 +}
562 +
563 +static void qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device *nand)
564 +{
565 + struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
566 +
567 + kfree(ecc_cfg);
568 +}
569 +
570 +static int qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device *nand,
571 + struct nand_page_io_req *req)
572 +{
573 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
574 + struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
575 +
576 + snandc->qspi->ecc = ecc_cfg;
577 + snandc->qspi->raw_rw = false;
578 + snandc->qspi->oob_rw = false;
579 + snandc->qspi->page_rw = false;
580 +
581 + if (req->datalen)
582 + snandc->qspi->page_rw = true;
583 +
584 + if (req->ooblen)
585 + snandc->qspi->oob_rw = true;
586 +
587 + if (req->mode == MTD_OPS_RAW)
588 + snandc->qspi->raw_rw = true;
589 +
590 + return 0;
591 +}
592 +
593 +static int qcom_spi_ecc_finish_io_req_pipelined(struct nand_device *nand,
594 + struct nand_page_io_req *req)
595 +{
596 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
597 + struct mtd_info *mtd = nanddev_to_mtd(nand);
598 +
599 + if (req->mode == MTD_OPS_RAW || req->type != NAND_PAGE_READ)
600 + return 0;
601 +
602 + if (snandc->qspi->ecc_stats.failed)
603 + mtd->ecc_stats.failed += snandc->qspi->ecc_stats.failed;
604 + else
605 + mtd->ecc_stats.corrected += snandc->qspi->ecc_stats.corrected;
606 +
607 + if (snandc->qspi->ecc_stats.failed)
608 + return -EBADMSG;
609 + else
610 + return snandc->qspi->ecc_stats.bitflips;
611 +}
612 +
613 +static struct nand_ecc_engine_ops qcom_spi_ecc_engine_ops_pipelined = {
614 + .init_ctx = qcom_spi_ecc_init_ctx_pipelined,
615 + .cleanup_ctx = qcom_spi_ecc_cleanup_ctx_pipelined,
616 + .prepare_io_req = qcom_spi_ecc_prepare_io_req_pipelined,
617 + .finish_io_req = qcom_spi_ecc_finish_io_req_pipelined,
618 +};
619 +
620 +/* helper to configure location register values */
621 +static void qcom_spi_set_read_loc(struct qcom_nand_controller *snandc, int cw, int reg,
622 + int cw_offset, int read_size, int is_last_read_loc)
623 +{
624 + int reg_base = NAND_READ_LOCATION_0;
625 + int num_cw = snandc->qspi->num_cw;
626 +
627 + if (cw == (num_cw - 1))
628 + reg_base = NAND_READ_LOCATION_LAST_CW_0;
629 +
630 + reg_base += reg * 4;
631 +
632 + if (cw == (num_cw - 1))
633 + return qcom_spi_set_read_loc_last(snandc, reg_base, cw_offset,
634 + read_size, is_last_read_loc);
635 + else
636 + return qcom_spi_set_read_loc_first(snandc, reg_base, cw_offset,
637 + read_size, is_last_read_loc);
638 +}
639 +
640 +static void
641 +qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int cw)
642 +{
643 + __le32 *reg = &snandc->regs->read_location0;
644 + int num_cw = snandc->qspi->num_cw;
645 +
646 + qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL);
647 + if (cw == (num_cw - 1)) {
648 + reg = &snandc->regs->read_location_last0;
649 + qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4,
650 + NAND_BAM_NEXT_SGL);
651 + }
652 +
653 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
654 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
655 +
656 + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0);
657 + qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1,
658 + NAND_BAM_NEXT_SGL);
659 +}
660 +
661 +static int qcom_spi_block_erase(struct qcom_nand_controller *snandc)
662 +{
663 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
664 + int ret;
665 +
666 + snandc->buf_count = 0;
667 + snandc->buf_start = 0;
668 + qcom_clear_read_regs(snandc);
669 + qcom_clear_bam_transaction(snandc);
670 +
671 + snandc->regs->cmd = snandc->qspi->cmd;
672 + snandc->regs->addr0 = snandc->qspi->addr1;
673 + snandc->regs->addr1 = snandc->qspi->addr2;
674 + snandc->regs->cfg0 = cpu_to_le32(ecc_cfg->cfg0_raw & ~(7 << CW_PER_PAGE));
675 + snandc->regs->cfg1 = cpu_to_le32(ecc_cfg->cfg1_raw);
676 + snandc->regs->exec = cpu_to_le32(1);
677 +
678 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
679 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
680 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
681 +
682 + ret = qcom_submit_descs(snandc);
683 + if (ret) {
684 + dev_err(snandc->dev, "failure to erase block\n");
685 + return ret;
686 + }
687 +
688 + return 0;
689 +}
690 +
691 +static void qcom_spi_config_single_cw_page_read(struct qcom_nand_controller *snandc,
692 + bool use_ecc, int cw)
693 +{
694 + __le32 *reg = &snandc->regs->read_location0;
695 + int num_cw = snandc->qspi->num_cw;
696 +
697 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
698 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
699 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
700 + NAND_ERASED_CW_DETECT_CFG, 1, 0);
701 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
702 + NAND_ERASED_CW_DETECT_CFG, 1,
703 + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
704 +
705 + if (cw == (num_cw - 1)) {
706 + reg = &snandc->regs->read_location_last0;
707 + qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, NAND_BAM_NEXT_SGL);
708 + }
709 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
710 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
711 +
712 + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, 0);
713 +}
714 +
715 +static int qcom_spi_read_last_cw(struct qcom_nand_controller *snandc,
716 + const struct spi_mem_op *op)
717 +{
718 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
719 + struct mtd_info *mtd = snandc->qspi->mtd;
720 + int size, ret = 0;
721 + int col, bbpos;
722 + u32 cfg0, cfg1, ecc_bch_cfg;
723 + u32 num_cw = snandc->qspi->num_cw;
724 +
725 + qcom_clear_bam_transaction(snandc);
726 + qcom_clear_read_regs(snandc);
727 +
728 + size = ecc_cfg->cw_size;
729 + col = ecc_cfg->cw_size * (num_cw - 1);
730 +
731 + memset(snandc->data_buffer, 0xff, size);
732 + snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
733 + snandc->regs->addr1 = snandc->qspi->addr2;
734 +
735 + cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
736 + 0 << CW_PER_PAGE;
737 + cfg1 = ecc_cfg->cfg1_raw;
738 + ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
739 +
740 + snandc->regs->cmd = snandc->qspi->cmd;
741 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
742 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
743 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
744 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
745 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
746 + snandc->regs->exec = cpu_to_le32(1);
747 +
748 + qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1);
749 +
750 + qcom_spi_config_single_cw_page_read(snandc, false, num_cw - 1);
751 +
752 + qcom_read_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, size, 0);
753 +
754 + ret = qcom_submit_descs(snandc);
755 + if (ret) {
756 + dev_err(snandc->dev, "failed to read last cw\n");
757 + return ret;
758 + }
759 +
760 + qcom_nandc_dev_to_mem(snandc, true);
761 + u32 flash = le32_to_cpu(snandc->reg_read_buf[0]);
762 +
763 + if (flash & (FS_OP_ERR | FS_MPU_ERR))
764 + return -EIO;
765 +
766 + bbpos = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
767 +
768 + if (snandc->data_buffer[bbpos] == 0xff)
769 + snandc->data_buffer[bbpos + 1] = 0xff;
770 + if (snandc->data_buffer[bbpos] != 0xff)
771 + snandc->data_buffer[bbpos + 1] = snandc->data_buffer[bbpos];
772 +
773 + memcpy(op->data.buf.in, snandc->data_buffer + bbpos, op->data.nbytes);
774 +
775 + return ret;
776 +}
777 +
778 +static int qcom_spi_check_error(struct qcom_nand_controller *snandc, u8 *data_buf, u8 *oob_buf)
779 +{
780 + struct snandc_read_status *buf;
781 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
782 + int i, num_cw = snandc->qspi->num_cw;
783 + bool flash_op_err = false, erased;
784 + unsigned int max_bitflips = 0;
785 + unsigned int uncorrectable_cws = 0;
786 +
787 + snandc->qspi->ecc_stats.failed = 0;
788 + snandc->qspi->ecc_stats.corrected = 0;
789 +
790 + qcom_nandc_dev_to_mem(snandc, true);
791 + buf = (struct snandc_read_status *)snandc->reg_read_buf;
792 +
793 + for (i = 0; i < num_cw; i++, buf++) {
794 + u32 flash, buffer, erased_cw;
795 + int data_len, oob_len;
796 +
797 + if (i == (num_cw - 1)) {
798 + data_len = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
799 + oob_len = num_cw << 2;
800 + } else {
801 + data_len = ecc_cfg->cw_data;
802 + oob_len = 0;
803 + }
804 +
805 + flash = le32_to_cpu(buf->snandc_flash);
806 + buffer = le32_to_cpu(buf->snandc_buffer);
807 + erased_cw = le32_to_cpu(buf->snandc_erased_cw);
808 +
809 + if ((flash & FS_OP_ERR) && (buffer & BS_UNCORRECTABLE_BIT)) {
810 + if (ecc_cfg->bch_enabled)
811 + erased = (erased_cw & ERASED_CW) == ERASED_CW;
812 + else
813 + erased = false;
814 +
815 + if (!erased)
816 + uncorrectable_cws |= BIT(i);
817 +
818 + } else if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
819 + flash_op_err = true;
820 + } else {
821 + unsigned int stat;
822 +
823 + stat = buffer & BS_CORRECTABLE_ERR_MSK;
824 + snandc->qspi->ecc_stats.corrected += stat;
825 + max_bitflips = max(max_bitflips, stat);
826 + }
827 +
828 + if (data_buf)
829 + data_buf += data_len;
830 + if (oob_buf)
831 + oob_buf += oob_len + ecc_cfg->bytes;
832 + }
833 +
834 + if (flash_op_err)
835 + return -EIO;
836 +
837 + if (!uncorrectable_cws)
838 + snandc->qspi->ecc_stats.bitflips = max_bitflips;
839 + else
840 + snandc->qspi->ecc_stats.failed++;
841 +
842 + return 0;
843 +}
844 +
845 +static int qcom_spi_check_raw_flash_errors(struct qcom_nand_controller *snandc, int cw_cnt)
846 +{
847 + int i;
848 +
849 + qcom_nandc_dev_to_mem(snandc, true);
850 +
851 + for (i = 0; i < cw_cnt; i++) {
852 + u32 flash = le32_to_cpu(snandc->reg_read_buf[i]);
853 +
854 + if (flash & (FS_OP_ERR | FS_MPU_ERR))
855 + return -EIO;
856 + }
857 +
858 + return 0;
859 +}
860 +
861 +static int qcom_spi_read_cw_raw(struct qcom_nand_controller *snandc, u8 *data_buf,
862 + u8 *oob_buf, int cw)
863 +{
864 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
865 + struct mtd_info *mtd = snandc->qspi->mtd;
866 + int data_size1, data_size2, oob_size1, oob_size2;
867 + int ret, reg_off = FLASH_BUF_ACC, read_loc = 0;
868 + int raw_cw = cw;
869 + u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
870 + int col;
871 +
872 + snandc->buf_count = 0;
873 + snandc->buf_start = 0;
874 + qcom_clear_read_regs(snandc);
875 + qcom_clear_bam_transaction(snandc);
876 + raw_cw = num_cw - 1;
877 +
878 + cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
879 + 0 << CW_PER_PAGE;
880 + cfg1 = ecc_cfg->cfg1_raw;
881 + ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
882 +
883 + col = ecc_cfg->cw_size * cw;
884 +
885 + snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
886 + snandc->regs->addr1 = snandc->qspi->addr2;
887 + snandc->regs->cmd = snandc->qspi->cmd;
888 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
889 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
890 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
891 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
892 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
893 + snandc->regs->exec = cpu_to_le32(1);
894 +
895 + qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1);
896 +
897 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
898 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
899 + qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0);
900 +
901 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
902 + NAND_ERASED_CW_DETECT_CFG, 1, 0);
903 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
904 + NAND_ERASED_CW_DETECT_CFG, 1,
905 + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
906 +
907 + data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
908 + oob_size1 = ecc_cfg->bbm_size;
909 +
910 + if (cw == (num_cw - 1)) {
911 + data_size2 = NANDC_STEP_SIZE - data_size1 -
912 + ((num_cw - 1) * 4);
913 + oob_size2 = (num_cw * 4) + ecc_cfg->ecc_bytes_hw +
914 + ecc_cfg->spare_bytes;
915 + } else {
916 + data_size2 = ecc_cfg->cw_data - data_size1;
917 + oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
918 + }
919 +
920 + qcom_spi_set_read_loc(snandc, cw, 0, read_loc, data_size1, 0);
921 + read_loc += data_size1;
922 +
923 + qcom_spi_set_read_loc(snandc, cw, 1, read_loc, oob_size1, 0);
924 + read_loc += oob_size1;
925 +
926 + qcom_spi_set_read_loc(snandc, cw, 2, read_loc, data_size2, 0);
927 + read_loc += data_size2;
928 +
929 + qcom_spi_set_read_loc(snandc, cw, 3, read_loc, oob_size2, 1);
930 +
931 + qcom_spi_config_cw_read(snandc, false, raw_cw);
932 +
933 + qcom_read_data_dma(snandc, reg_off, data_buf, data_size1, 0);
934 + reg_off += data_size1;
935 +
936 + qcom_read_data_dma(snandc, reg_off, oob_buf, oob_size1, 0);
937 + reg_off += oob_size1;
938 +
939 + qcom_read_data_dma(snandc, reg_off, data_buf + data_size1, data_size2, 0);
940 + reg_off += data_size2;
941 +
942 + qcom_read_data_dma(snandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
943 +
944 + ret = qcom_submit_descs(snandc);
945 + if (ret) {
946 + dev_err(snandc->dev, "failure to read raw cw %d\n", cw);
947 + return ret;
948 + }
949 +
950 + return qcom_spi_check_raw_flash_errors(snandc, 1);
951 +}
952 +
953 +static int qcom_spi_read_page_raw(struct qcom_nand_controller *snandc,
954 + const struct spi_mem_op *op)
955 +{
956 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
957 + u8 *data_buf = NULL, *oob_buf = NULL;
958 + int ret, cw;
959 + u32 num_cw = snandc->qspi->num_cw;
960 +
961 + if (snandc->qspi->page_rw)
962 + data_buf = op->data.buf.in;
963 +
964 + oob_buf = snandc->qspi->oob_buf;
965 + memset(oob_buf, 0xff, OOB_BUF_SIZE);
966 +
967 + for (cw = 0; cw < num_cw; cw++) {
968 + ret = qcom_spi_read_cw_raw(snandc, data_buf, oob_buf, cw);
969 + if (ret)
970 + return ret;
971 +
972 + if (data_buf)
973 + data_buf += ecc_cfg->cw_data;
974 + if (oob_buf)
975 + oob_buf += ecc_cfg->bytes;
976 + }
977 +
978 + return 0;
979 +}
980 +
981 +static int qcom_spi_read_page_ecc(struct qcom_nand_controller *snandc,
982 + const struct spi_mem_op *op)
983 +{
984 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
985 + u8 *data_buf = NULL, *data_buf_start, *oob_buf = NULL, *oob_buf_start;
986 + int ret, i;
987 + u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
988 +
989 + data_buf = op->data.buf.in;
990 + data_buf_start = data_buf;
991 +
992 + oob_buf = snandc->qspi->oob_buf;
993 + oob_buf_start = oob_buf;
994 +
995 + snandc->buf_count = 0;
996 + snandc->buf_start = 0;
997 + qcom_clear_read_regs(snandc);
998 +
999 + cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
1000 + (num_cw - 1) << CW_PER_PAGE;
1001 + cfg1 = ecc_cfg->cfg1;
1002 + ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1003 +
1004 + snandc->regs->addr0 = snandc->qspi->addr1;
1005 + snandc->regs->addr1 = snandc->qspi->addr2;
1006 + snandc->regs->cmd = snandc->qspi->cmd;
1007 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
1008 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
1009 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1010 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
1011 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
1012 + snandc->regs->exec = cpu_to_le32(1);
1013 +
1014 + qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
1015 +
1016 + qcom_clear_bam_transaction(snandc);
1017 +
1018 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
1019 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
1020 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
1021 + NAND_ERASED_CW_DETECT_CFG, 1, 0);
1022 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
1023 + NAND_ERASED_CW_DETECT_CFG, 1,
1024 + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
1025 +
1026 + for (i = 0; i < num_cw; i++) {
1027 + int data_size, oob_size;
1028 +
1029 + if (i == (num_cw - 1)) {
1030 + data_size = 512 - ((num_cw - 1) << 2);
1031 + oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1032 + ecc_cfg->spare_bytes;
1033 + } else {
1034 + data_size = ecc_cfg->cw_data;
1035 + oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
1036 + }
1037 +
1038 + if (data_buf && oob_buf) {
1039 + qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 0);
1040 + qcom_spi_set_read_loc(snandc, i, 1, data_size, oob_size, 1);
1041 + } else if (data_buf) {
1042 + qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 1);
1043 + } else {
1044 + qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
1045 + }
1046 +
1047 + qcom_spi_config_cw_read(snandc, true, i);
1048 +
1049 + if (data_buf)
1050 + qcom_read_data_dma(snandc, FLASH_BUF_ACC, data_buf,
1051 + data_size, 0);
1052 + if (oob_buf) {
1053 + int j;
1054 +
1055 + for (j = 0; j < ecc_cfg->bbm_size; j++)
1056 + *oob_buf++ = 0xff;
1057 +
1058 + qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
1059 + oob_buf, oob_size, 0);
1060 + }
1061 +
1062 + if (data_buf)
1063 + data_buf += data_size;
1064 + if (oob_buf)
1065 + oob_buf += oob_size;
1066 + }
1067 +
1068 + ret = qcom_submit_descs(snandc);
1069 + if (ret) {
1070 + dev_err(snandc->dev, "failure to read page\n");
1071 + return ret;
1072 + }
1073 +
1074 + return qcom_spi_check_error(snandc, data_buf_start, oob_buf_start);
1075 +}
1076 +
1077 +static int qcom_spi_read_page_oob(struct qcom_nand_controller *snandc,
1078 + const struct spi_mem_op *op)
1079 +{
1080 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1081 + u8 *data_buf = NULL, *data_buf_start, *oob_buf = NULL, *oob_buf_start;
1082 + int ret, i;
1083 + u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
1084 +
1085 + oob_buf = op->data.buf.in;
1086 + oob_buf_start = oob_buf;
1087 +
1088 + data_buf_start = data_buf;
1089 +
1090 + snandc->buf_count = 0;
1091 + snandc->buf_start = 0;
1092 + qcom_clear_read_regs(snandc);
1093 + qcom_clear_bam_transaction(snandc);
1094 +
1095 + cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
1096 + (num_cw - 1) << CW_PER_PAGE;
1097 + cfg1 = ecc_cfg->cfg1;
1098 + ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1099 +
1100 + snandc->regs->addr0 = snandc->qspi->addr1;
1101 + snandc->regs->addr1 = snandc->qspi->addr2;
1102 + snandc->regs->cmd = snandc->qspi->cmd;
1103 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
1104 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
1105 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1106 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
1107 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
1108 + snandc->regs->exec = cpu_to_le32(1);
1109 +
1110 + qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
1111 +
1112 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
1113 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
1114 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
1115 + NAND_ERASED_CW_DETECT_CFG, 1, 0);
1116 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
1117 + NAND_ERASED_CW_DETECT_CFG, 1,
1118 + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
1119 +
1120 + for (i = 0; i < num_cw; i++) {
1121 + int data_size, oob_size;
1122 +
1123 + if (i == (num_cw - 1)) {
1124 + data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1125 + oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1126 + ecc_cfg->spare_bytes;
1127 + } else {
1128 + data_size = ecc_cfg->cw_data;
1129 + oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
1130 + }
1131 +
1132 + qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
1133 +
1134 + qcom_spi_config_cw_read(snandc, true, i);
1135 +
1136 + if (oob_buf) {
1137 + int j;
1138 +
1139 + for (j = 0; j < ecc_cfg->bbm_size; j++)
1140 + *oob_buf++ = 0xff;
1141 +
1142 + qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
1143 + oob_buf, oob_size, 0);
1144 + }
1145 +
1146 + if (oob_buf)
1147 + oob_buf += oob_size;
1148 + }
1149 +
1150 + ret = qcom_submit_descs(snandc);
1151 + if (ret) {
1152 + dev_err(snandc->dev, "failure to read oob\n");
1153 + return ret;
1154 + }
1155 +
1156 + return qcom_spi_check_error(snandc, data_buf_start, oob_buf_start);
1157 +}
1158 +
1159 +static int qcom_spi_read_page(struct qcom_nand_controller *snandc,
1160 + const struct spi_mem_op *op)
1161 +{
1162 + if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
1163 + return qcom_spi_read_page_raw(snandc, op);
1164 +
1165 + if (snandc->qspi->page_rw)
1166 + return qcom_spi_read_page_ecc(snandc, op);
1167 +
1168 + if (snandc->qspi->oob_rw && snandc->qspi->raw_rw)
1169 + return qcom_spi_read_last_cw(snandc, op);
1170 +
1171 + if (snandc->qspi->oob_rw)
1172 + return qcom_spi_read_page_oob(snandc, op);
1173 +
1174 + return 0;
1175 +}
1176 +
1177 +static void qcom_spi_config_page_write(struct qcom_nand_controller *snandc)
1178 +{
1179 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
1180 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
1181 + qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG,
1182 + 1, NAND_BAM_NEXT_SGL);
1183 +}
1184 +
1185 +static void qcom_spi_config_cw_write(struct qcom_nand_controller *snandc)
1186 +{
1187 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
1188 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1189 + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1190 +
1191 + qcom_write_reg_dma(snandc, &snandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0);
1192 + qcom_write_reg_dma(snandc, &snandc->regs->clrreadstatus, NAND_READ_STATUS, 1,
1193 + NAND_BAM_NEXT_SGL);
1194 +}
1195 +
1196 +static int qcom_spi_program_raw(struct qcom_nand_controller *snandc,
1197 + const struct spi_mem_op *op)
1198 +{
1199 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1200 + struct mtd_info *mtd = snandc->qspi->mtd;
1201 + u8 *data_buf = NULL, *oob_buf = NULL;
1202 + int i, ret;
1203 + int num_cw = snandc->qspi->num_cw;
1204 + u32 cfg0, cfg1, ecc_bch_cfg;
1205 +
1206 + cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
1207 + (num_cw - 1) << CW_PER_PAGE;
1208 + cfg1 = ecc_cfg->cfg1_raw;
1209 + ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
1210 +
1211 + data_buf = snandc->qspi->data_buf;
1212 +
1213 + oob_buf = snandc->qspi->oob_buf;
1214 + memset(oob_buf, 0xff, OOB_BUF_SIZE);
1215 +
1216 + snandc->buf_count = 0;
1217 + snandc->buf_start = 0;
1218 + qcom_clear_read_regs(snandc);
1219 + qcom_clear_bam_transaction(snandc);
1220 +
1221 + snandc->regs->addr0 = snandc->qspi->addr1;
1222 + snandc->regs->addr1 = snandc->qspi->addr2;
1223 + snandc->regs->cmd = snandc->qspi->cmd;
1224 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
1225 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
1226 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1227 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
1228 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
1229 + snandc->regs->exec = cpu_to_le32(1);
1230 +
1231 + qcom_spi_config_page_write(snandc);
1232 +
1233 + for (i = 0; i < num_cw; i++) {
1234 + int data_size1, data_size2, oob_size1, oob_size2;
1235 + int reg_off = FLASH_BUF_ACC;
1236 +
1237 + data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
1238 + oob_size1 = ecc_cfg->bbm_size;
1239 +
1240 + if (i == (num_cw - 1)) {
1241 + data_size2 = NANDC_STEP_SIZE - data_size1 -
1242 + ((num_cw - 1) << 2);
1243 + oob_size2 = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1244 + ecc_cfg->spare_bytes;
1245 + } else {
1246 + data_size2 = ecc_cfg->cw_data - data_size1;
1247 + oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
1248 + }
1249 +
1250 + qcom_write_data_dma(snandc, reg_off, data_buf, data_size1,
1251 + NAND_BAM_NO_EOT);
1252 + reg_off += data_size1;
1253 + data_buf += data_size1;
1254 +
1255 + qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size1,
1256 + NAND_BAM_NO_EOT);
1257 + oob_buf += oob_size1;
1258 + reg_off += oob_size1;
1259 +
1260 + qcom_write_data_dma(snandc, reg_off, data_buf, data_size2,
1261 + NAND_BAM_NO_EOT);
1262 + reg_off += data_size2;
1263 + data_buf += data_size2;
1264 +
1265 + qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size2, 0);
1266 + oob_buf += oob_size2;
1267 +
1268 + qcom_spi_config_cw_write(snandc);
1269 + }
1270 +
1271 + ret = qcom_submit_descs(snandc);
1272 + if (ret) {
1273 + dev_err(snandc->dev, "failure to write raw page\n");
1274 + return ret;
1275 + }
1276 +
1277 + return 0;
1278 +}
1279 +
1280 +static int qcom_spi_program_ecc(struct qcom_nand_controller *snandc,
1281 + const struct spi_mem_op *op)
1282 +{
1283 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1284 + u8 *data_buf = NULL, *oob_buf = NULL;
1285 + int i, ret;
1286 + int num_cw = snandc->qspi->num_cw;
1287 + u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1288 +
1289 + cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
1290 + (num_cw - 1) << CW_PER_PAGE;
1291 + cfg1 = ecc_cfg->cfg1;
1292 + ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1293 + ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1294 +
1295 + if (snandc->qspi->data_buf)
1296 + data_buf = snandc->qspi->data_buf;
1297 +
1298 + oob_buf = snandc->qspi->oob_buf;
1299 +
1300 + snandc->buf_count = 0;
1301 + snandc->buf_start = 0;
1302 + qcom_clear_read_regs(snandc);
1303 + qcom_clear_bam_transaction(snandc);
1304 +
1305 + snandc->regs->addr0 = snandc->qspi->addr1;
1306 + snandc->regs->addr1 = snandc->qspi->addr2;
1307 + snandc->regs->cmd = snandc->qspi->cmd;
1308 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
1309 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
1310 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1311 + snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1312 + snandc->regs->exec = cpu_to_le32(1);
1313 +
1314 + qcom_spi_config_page_write(snandc);
1315 +
1316 + for (i = 0; i < num_cw; i++) {
1317 + int data_size, oob_size;
1318 +
1319 + if (i == (num_cw - 1)) {
1320 + data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1321 + oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1322 + ecc_cfg->spare_bytes;
1323 + } else {
1324 + data_size = ecc_cfg->cw_data;
1325 + oob_size = ecc_cfg->bytes;
1326 + }
1327 +
1328 + if (data_buf)
1329 + qcom_write_data_dma(snandc, FLASH_BUF_ACC, data_buf, data_size,
1330 + i == (num_cw - 1) ? NAND_BAM_NO_EOT : 0);
1331 +
1332 + if (i == (num_cw - 1)) {
1333 + if (oob_buf) {
1334 + oob_buf += ecc_cfg->bbm_size;
1335 + qcom_write_data_dma(snandc, FLASH_BUF_ACC + data_size,
1336 + oob_buf, oob_size, 0);
1337 + }
1338 + }
1339 +
1340 + qcom_spi_config_cw_write(snandc);
1341 +
1342 + if (data_buf)
1343 + data_buf += data_size;
1344 + if (oob_buf)
1345 + oob_buf += oob_size;
1346 + }
1347 +
1348 + ret = qcom_submit_descs(snandc);
1349 + if (ret) {
1350 + dev_err(snandc->dev, "failure to write page\n");
1351 + return ret;
1352 + }
1353 +
1354 + return 0;
1355 +}
1356 +
1357 +static int qcom_spi_program_oob(struct qcom_nand_controller *snandc,
1358 + const struct spi_mem_op *op)
1359 +{
1360 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1361 + u8 *oob_buf = NULL;
1362 + int ret, col, data_size, oob_size;
1363 + int num_cw = snandc->qspi->num_cw;
1364 + u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1365 +
1366 + cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
1367 + (num_cw - 1) << CW_PER_PAGE;
1368 + cfg1 = ecc_cfg->cfg1;
1369 + ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1370 + ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1371 +
1372 + col = ecc_cfg->cw_size * (num_cw - 1);
1373 +
1374 + oob_buf = snandc->qspi->data_buf;
1375 +
1376 + snandc->buf_count = 0;
1377 + snandc->buf_start = 0;
1378 + qcom_clear_read_regs(snandc);
1379 + qcom_clear_bam_transaction(snandc);
1380 + snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
1381 + snandc->regs->addr1 = snandc->qspi->addr2;
1382 + snandc->regs->cmd = snandc->qspi->cmd;
1383 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
1384 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
1385 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1386 + snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1387 + snandc->regs->exec = cpu_to_le32(1);
1388 +
1389 + /* calculate the data and oob size for the last codeword/step */
1390 + data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1391 + oob_size = snandc->qspi->mtd->oobavail;
1392 +
1393 + memset(snandc->data_buffer, 0xff, ecc_cfg->cw_data);
1394 + /* override new oob content to last codeword */
1395 + mtd_ooblayout_get_databytes(snandc->qspi->mtd, snandc->data_buffer + data_size,
1396 + oob_buf, 0, snandc->qspi->mtd->oobavail);
1397 + qcom_spi_config_page_write(snandc);
1398 + qcom_write_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, data_size + oob_size, 0);
1399 + qcom_spi_config_cw_write(snandc);
1400 +
1401 + ret = qcom_submit_descs(snandc);
1402 + if (ret) {
1403 + dev_err(snandc->dev, "failure to write oob\n");
1404 + return ret;
1405 + }
1406 +
1407 + return 0;
1408 +}
1409 +
1410 +static int qcom_spi_program_execute(struct qcom_nand_controller *snandc,
1411 + const struct spi_mem_op *op)
1412 +{
1413 + if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
1414 + return qcom_spi_program_raw(snandc, op);
1415 +
1416 + if (snandc->qspi->page_rw)
1417 + return qcom_spi_program_ecc(snandc, op);
1418 +
1419 + if (snandc->qspi->oob_rw)
1420 + return qcom_spi_program_oob(snandc, op);
1421 +
1422 + return 0;
1423 +}
1424 +
1425 +static u32 qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode)
1426 +{
1427 + u32 cmd = 0x0;
1428 +
1429 + switch (opcode) {
1430 + case SPINAND_RESET:
1431 + cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE);
1432 + break;
1433 + case SPINAND_READID:
1434 + cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID);
1435 + break;
1436 + case SPINAND_GET_FEATURE:
1437 + cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE);
1438 + break;
1439 + case SPINAND_SET_FEATURE:
1440 + cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE |
1441 + QPIC_SET_FEATURE);
1442 + break;
1443 + case SPINAND_READ:
1444 + if (snandc->qspi->raw_rw) {
1445 + cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1446 + SPI_WP | SPI_HOLD | OP_PAGE_READ);
1447 + } else {
1448 + cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1449 + SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC);
1450 + }
1451 +
1452 + break;
1453 + case SPINAND_ERASE:
1454 + cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP |
1455 + SPI_HOLD | SPI_TRANSFER_MODE_x1;
1456 + break;
1457 + case SPINAND_WRITE_EN:
1458 + cmd = SPINAND_WRITE_EN;
1459 + break;
1460 + case SPINAND_PROGRAM_EXECUTE:
1461 + cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1462 + SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
1463 + break;
1464 + case SPINAND_PROGRAM_LOAD:
1465 + cmd = SPINAND_PROGRAM_LOAD;
1466 + break;
1467 + default:
1468 + dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
1469 + return -EOPNOTSUPP;
1470 + }
1471 +
1472 + return cmd;
1473 +}
1474 +
1475 +static int qcom_spi_write_page(struct qcom_nand_controller *snandc,
1476 + const struct spi_mem_op *op)
1477 +{
1478 + struct qpic_snand_op s_op = {};
1479 + u32 cmd;
1480 +
1481 + cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode);
1482 + if (cmd < 0)
1483 + return cmd;
1484 +
1485 + s_op.cmd_reg = cmd;
1486 +
1487 + if (op->cmd.opcode == SPINAND_PROGRAM_LOAD)
1488 + snandc->qspi->data_buf = (u8 *)op->data.buf.out;
1489 +
1490 + return 0;
1491 +}
1492 +
1493 +static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc,
1494 + const struct spi_mem_op *op)
1495 +{
1496 + struct qpic_snand_op s_op = {};
1497 + u32 cmd;
1498 + int ret, opcode;
1499 +
1500 + cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode);
1501 + if (cmd < 0)
1502 + return cmd;
1503 +
1504 + s_op.cmd_reg = cmd;
1505 + s_op.addr1_reg = op->addr.val;
1506 + s_op.addr2_reg = 0;
1507 +
1508 + opcode = op->cmd.opcode;
1509 +
1510 + switch (opcode) {
1511 + case SPINAND_WRITE_EN:
1512 + return 0;
1513 + case SPINAND_PROGRAM_EXECUTE:
1514 + s_op.addr1_reg = op->addr.val << 16;
1515 + s_op.addr2_reg = op->addr.val >> 16 & 0xff;
1516 + snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
1517 + snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1518 + snandc->qspi->cmd = cpu_to_le32(cmd);
1519 + return qcom_spi_program_execute(snandc, op);
1520 + case SPINAND_READ:
1521 + s_op.addr1_reg = (op->addr.val << 16);
1522 + s_op.addr2_reg = op->addr.val >> 16 & 0xff;
1523 + snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
1524 + snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1525 + snandc->qspi->cmd = cpu_to_le32(cmd);
1526 + return 0;
1527 + case SPINAND_ERASE:
1528 + s_op.addr2_reg = (op->addr.val >> 16) & 0xffff;
1529 + s_op.addr1_reg = op->addr.val;
1530 + snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg << 16);
1531 + snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1532 + snandc->qspi->cmd = cpu_to_le32(cmd);
1533 + qcom_spi_block_erase(snandc);
1534 + return 0;
1535 + default:
1536 + break;
1537 + }
1538 +
1539 + snandc->buf_count = 0;
1540 + snandc->buf_start = 0;
1541 + qcom_clear_read_regs(snandc);
1542 + qcom_clear_bam_transaction(snandc);
1543 +
1544 + snandc->regs->cmd = cpu_to_le32(s_op.cmd_reg);
1545 + snandc->regs->exec = cpu_to_le32(1);
1546 + snandc->regs->addr0 = cpu_to_le32(s_op.addr1_reg);
1547 + snandc->regs->addr1 = cpu_to_le32(s_op.addr2_reg);
1548 +
1549 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
1550 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1551 +
1552 + ret = qcom_submit_descs(snandc);
1553 + if (ret)
1554 + dev_err(snandc->dev, "failure in submitting cmd descriptor\n");
1555 +
1556 + return ret;
1557 +}
1558 +
1559 +static int qcom_spi_io_op(struct qcom_nand_controller *snandc, const struct spi_mem_op *op)
1560 +{
1561 + int ret, val, opcode;
1562 + bool copy = false, copy_ftr = false;
1563 +
1564 + ret = qcom_spi_send_cmdaddr(snandc, op);
1565 + if (ret)
1566 + return ret;
1567 +
1568 + snandc->buf_count = 0;
1569 + snandc->buf_start = 0;
1570 + qcom_clear_read_regs(snandc);
1571 + qcom_clear_bam_transaction(snandc);
1572 + opcode = op->cmd.opcode;
1573 +
1574 + switch (opcode) {
1575 + case SPINAND_READID:
1576 + snandc->buf_count = 4;
1577 + qcom_read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
1578 + copy = true;
1579 + break;
1580 + case SPINAND_GET_FEATURE:
1581 + snandc->buf_count = 4;
1582 + qcom_read_reg_dma(snandc, NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1583 + copy_ftr = true;
1584 + break;
1585 + case SPINAND_SET_FEATURE:
1586 + snandc->regs->flash_feature = cpu_to_le32(*(u32 *)op->data.buf.out);
1587 + qcom_write_reg_dma(snandc, &snandc->regs->flash_feature,
1588 + NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1589 + break;
1590 + case SPINAND_PROGRAM_EXECUTE:
1591 + case SPINAND_WRITE_EN:
1592 + case SPINAND_RESET:
1593 + case SPINAND_ERASE:
1594 + case SPINAND_READ:
1595 + return 0;
1596 + default:
1597 + return -EOPNOTSUPP;
1598 + }
1599 +
1600 + ret = qcom_submit_descs(snandc);
1601 + if (ret)
1602 + dev_err(snandc->dev, "failure in submitting descriptor for:%d\n", opcode);
1603 +
1604 + if (copy) {
1605 + qcom_nandc_dev_to_mem(snandc, true);
1606 + memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count);
1607 + }
1608 +
1609 + if (copy_ftr) {
1610 + qcom_nandc_dev_to_mem(snandc, true);
1611 + val = le32_to_cpu(*(__le32 *)snandc->reg_read_buf);
1612 + val >>= 8;
1613 + memcpy(op->data.buf.in, &val, snandc->buf_count);
1614 + }
1615 +
1616 + return ret;
1617 +}
1618 +
1619 +static bool qcom_spi_is_page_op(const struct spi_mem_op *op)
1620 +{
1621 + if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && op->addr.buswidth != 4)
1622 + return false;
1623 +
1624 + if (op->data.dir == SPI_MEM_DATA_IN) {
1625 + if (op->addr.buswidth == 4 && op->data.buswidth == 4)
1626 + return true;
1627 +
1628 + if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1629 + return true;
1630 +
1631 + } else if (op->data.dir == SPI_MEM_DATA_OUT) {
1632 + if (op->data.buswidth == 4)
1633 + return true;
1634 + if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1635 + return true;
1636 + }
1637 +
1638 + return false;
1639 +}
1640 +
1641 +static bool qcom_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
1642 +{
1643 + if (!spi_mem_default_supports_op(mem, op))
1644 + return false;
1645 +
1646 + if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
1647 + return false;
1648 +
1649 + if (qcom_spi_is_page_op(op))
1650 + return true;
1651 +
1652 + return ((!op->addr.nbytes || op->addr.buswidth == 1) &&
1653 + (!op->dummy.nbytes || op->dummy.buswidth == 1) &&
1654 + (!op->data.nbytes || op->data.buswidth == 1));
1655 +}
1656 +
1657 +static int qcom_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
1658 +{
1659 + struct qcom_nand_controller *snandc = spi_controller_get_devdata(mem->spi->controller);
1660 +
1661 + dev_dbg(snandc->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode,
1662 + op->addr.val, op->addr.buswidth, op->addr.nbytes,
1663 + op->data.buswidth, op->data.nbytes);
1664 +
1665 + if (qcom_spi_is_page_op(op)) {
1666 + if (op->data.dir == SPI_MEM_DATA_IN)
1667 + return qcom_spi_read_page(snandc, op);
1668 + if (op->data.dir == SPI_MEM_DATA_OUT)
1669 + return qcom_spi_write_page(snandc, op);
1670 + } else {
1671 + return qcom_spi_io_op(snandc, op);
1672 + }
1673 +
1674 + return 0;
1675 +}
1676 +
1677 +static const struct spi_controller_mem_ops qcom_spi_mem_ops = {
1678 + .supports_op = qcom_spi_supports_op,
1679 + .exec_op = qcom_spi_exec_op,
1680 +};
1681 +
1682 +static const struct spi_controller_mem_caps qcom_spi_mem_caps = {
1683 + .ecc = true,
1684 +};
1685 +
1686 +static int qcom_spi_probe(struct platform_device *pdev)
1687 +{
1688 + struct device *dev = &pdev->dev;
1689 + struct spi_controller *ctlr;
1690 + struct qcom_nand_controller *snandc;
1691 + struct qpic_spi_nand *qspi;
1692 + struct qpic_ecc *ecc;
1693 + struct resource *res;
1694 + const void *dev_data;
1695 + int ret;
1696 +
1697 + ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
1698 + if (!ecc)
1699 + return -ENOMEM;
1700 +
1701 + qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL);
1702 + if (!qspi)
1703 + return -ENOMEM;
1704 +
1705 + ctlr = __devm_spi_alloc_controller(dev, sizeof(*snandc), false);
1706 + if (!ctlr)
1707 + return -ENOMEM;
1708 +
1709 + platform_set_drvdata(pdev, ctlr);
1710 +
1711 + snandc = spi_controller_get_devdata(ctlr);
1712 + qspi->snandc = snandc;
1713 +
1714 + snandc->dev = dev;
1715 + snandc->qspi = qspi;
1716 + snandc->qspi->ctlr = ctlr;
1717 + snandc->qspi->ecc = ecc;
1718 +
1719 + dev_data = of_device_get_match_data(dev);
1720 + if (!dev_data) {
1721 + dev_err(&pdev->dev, "failed to get device data\n");
1722 + return -ENODEV;
1723 + }
1724 +
1725 + snandc->props = dev_data;
1726 + snandc->dev = &pdev->dev;
1727 +
1728 + snandc->core_clk = devm_clk_get(dev, "core");
1729 + if (IS_ERR(snandc->core_clk))
1730 + return PTR_ERR(snandc->core_clk);
1731 +
1732 + snandc->aon_clk = devm_clk_get(dev, "aon");
1733 + if (IS_ERR(snandc->aon_clk))
1734 + return PTR_ERR(snandc->aon_clk);
1735 +
1736 + snandc->qspi->iomacro_clk = devm_clk_get(dev, "iom");
1737 + if (IS_ERR(snandc->qspi->iomacro_clk))
1738 + return PTR_ERR(snandc->qspi->iomacro_clk);
1739 +
1740 + snandc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1741 + if (IS_ERR(snandc->base))
1742 + return PTR_ERR(snandc->base);
1743 +
1744 + snandc->base_phys = res->start;
1745 + snandc->base_dma = dma_map_resource(dev, res->start, resource_size(res),
1746 + DMA_BIDIRECTIONAL, 0);
1747 + if (dma_mapping_error(dev, snandc->base_dma))
1748 + return -ENXIO;
1749 +
1750 + ret = clk_prepare_enable(snandc->core_clk);
1751 + if (ret)
1752 + goto err_dis_core_clk;
1753 +
1754 + ret = clk_prepare_enable(snandc->aon_clk);
1755 + if (ret)
1756 + goto err_dis_aon_clk;
1757 +
1758 + ret = clk_prepare_enable(snandc->qspi->iomacro_clk);
1759 + if (ret)
1760 + goto err_dis_iom_clk;
1761 +
1762 + ret = qcom_nandc_alloc(snandc);
1763 + if (ret)
1764 + goto err_snand_alloc;
1765 +
1766 + ret = qcom_spi_init(snandc);
1767 + if (ret)
1768 + goto err_spi_init;
1769 +
1770 + /* setup ECC engine */
1771 + snandc->qspi->ecc_eng.dev = &pdev->dev;
1772 + snandc->qspi->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;
1773 + snandc->qspi->ecc_eng.ops = &qcom_spi_ecc_engine_ops_pipelined;
1774 + snandc->qspi->ecc_eng.priv = snandc;
1775 +
1776 + ret = nand_ecc_register_on_host_hw_engine(&snandc->qspi->ecc_eng);
1777 + if (ret) {
1778 + dev_err(&pdev->dev, "failed to register ecc engine:%d\n", ret);
1779 + goto err_spi_init;
1780 + }
1781 +
1782 + ctlr->num_chipselect = QPIC_QSPI_NUM_CS;
1783 + ctlr->mem_ops = &qcom_spi_mem_ops;
1784 + ctlr->mem_caps = &qcom_spi_mem_caps;
1785 + ctlr->dev.of_node = pdev->dev.of_node;
1786 + ctlr->mode_bits = SPI_TX_DUAL | SPI_RX_DUAL |
1787 + SPI_TX_QUAD | SPI_RX_QUAD;
1788 +
1789 + ret = spi_register_controller(ctlr);
1790 + if (ret) {
1791 + dev_err(&pdev->dev, "spi_register_controller failed.\n");
1792 + goto err_spi_init;
1793 + }
1794 +
1795 + return 0;
1796 +
1797 +err_spi_init:
1798 + qcom_nandc_unalloc(snandc);
1799 +err_snand_alloc:
1800 + clk_disable_unprepare(snandc->qspi->iomacro_clk);
1801 +err_dis_iom_clk:
1802 + clk_disable_unprepare(snandc->aon_clk);
1803 +err_dis_aon_clk:
1804 + clk_disable_unprepare(snandc->core_clk);
1805 +err_dis_core_clk:
1806 + dma_unmap_resource(dev, res->start, resource_size(res),
1807 + DMA_BIDIRECTIONAL, 0);
1808 + return ret;
1809 +}
1810 +
1811 +static void qcom_spi_remove(struct platform_device *pdev)
1812 +{
1813 + struct spi_controller *ctlr = platform_get_drvdata(pdev);
1814 + struct qcom_nand_controller *snandc = spi_controller_get_devdata(ctlr);
1815 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1816 +
1817 + spi_unregister_controller(ctlr);
1818 +
1819 + qcom_nandc_unalloc(snandc);
1820 +
1821 + clk_disable_unprepare(snandc->aon_clk);
1822 + clk_disable_unprepare(snandc->core_clk);
1823 + clk_disable_unprepare(snandc->qspi->iomacro_clk);
1824 +
1825 + dma_unmap_resource(&pdev->dev, snandc->base_dma, resource_size(res),
1826 + DMA_BIDIRECTIONAL, 0);
1827 +}
1828 +
1829 +static const struct qcom_nandc_props ipq9574_snandc_props = {
1830 + .dev_cmd_reg_start = 0x7000,
1831 + .supports_bam = true,
1832 +};
1833 +
1834 +static const struct of_device_id qcom_snandc_of_match[] = {
1835 + {
1836 + .compatible = "qcom,spi-qpic-snand",
1837 + .data = &ipq9574_snandc_props,
1838 + },
1839 + {}
1840 +}
1841 +MODULE_DEVICE_TABLE(of, qcom_snandc_of_match);
1842 +
1843 +static struct platform_driver qcom_spi_driver = {
1844 + .driver = {
1845 + .name = "qcom_snand",
1846 + .of_match_table = qcom_snandc_of_match,
1847 + },
1848 + .probe = qcom_spi_probe,
1849 + .remove_new = qcom_spi_remove,
1850 +};
1851 +module_platform_driver(qcom_spi_driver);
1852 +
1853 +MODULE_DESCRIPTION("SPI driver for QPIC QSPI cores");
1854 +MODULE_AUTHOR("Md Sadre Alam <quic_mdalam@quicinc.com>");
1855 +MODULE_LICENSE("GPL");
1856 +
1857 --- a/include/linux/mtd/nand-qpic-common.h
1858 +++ b/include/linux/mtd/nand-qpic-common.h
1859 @@ -322,6 +322,10 @@ struct nandc_regs {
1860 __le32 read_location_last1;
1861 __le32 read_location_last2;
1862 __le32 read_location_last3;
1863 + __le32 spi_cfg;
1864 + __le32 num_addr_cycle;
1865 + __le32 busy_wait_cnt;
1866 + __le32 flash_feature;
1867
1868 __le32 erased_cw_detect_cfg_clr;
1869 __le32 erased_cw_detect_cfg_set;
1870 @@ -336,6 +340,7 @@ struct nandc_regs {
1871 *
1872 * @core_clk: controller clock
1873 * @aon_clk: another controller clock
1874 + * @iomacro_clk: io macro clock
1875 *
1876 * @regs: a contiguous chunk of memory for DMA register
1877 * writes. contains the register values to be
1878 @@ -345,6 +350,7 @@ struct nandc_regs {
1879 * initialized via DT match data
1880 *
1881 * @controller: base controller structure
1882 + * @qspi: qpic spi structure
1883 * @host_list: list containing all the chips attached to the
1884 * controller
1885 *
1886 @@ -389,6 +395,7 @@ struct qcom_nand_controller {
1887 const struct qcom_nandc_props *props;
1888
1889 struct nand_controller *controller;
1890 + struct qpic_spi_nand *qspi;
1891 struct list_head host_list;
1892
1893 union {
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