git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From 830d8062d25581cf0beaa334486eea06834044da Mon Sep 17 00:00:00 2001
   2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   3 Date: Wed, 8 Jan 2025 10:36:36 +0100
   4 Subject: [PATCH] clk: ralink: mtmips: remove duplicated 'xtal' clock for
   5  Ralink SoC RT3883
   6
   7 Ralink SoC RT3883 has already 'xtal' defined as a base clock so there is no
   8 need to redefine it again in fixed clocks section. Hence, remove the duplicate
   9 one from there.
  10
  11 Fixes: d34db686a3d7 ("clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs")
  12 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  13 Link: https://lore.kernel.org/r/20250108093636.265033-1-sergio.paracuellos@gmail.com
  14 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  15 ---
  16  drivers/clk/ralink/clk-mtmips.c | 1 -
  17  1 file changed, 1 deletion(-)
  18
  19 --- a/drivers/clk/ralink/clk-mtmips.c
  20 +++ b/drivers/clk/ralink/clk-mtmips.c
  21 @@ -266,7 +266,6 @@ err_clk_unreg:
  22         }
  23
  24  static struct mtmips_clk_fixed rt3883_fixed_clocks[] = {
  25 -       CLK_FIXED("xtal", NULL, 40000000),
  26         CLK_FIXED("periph", "xtal", 40000000)
  27  };
  28