git.openwrt.org Git - openwrt/staging/svanheule.git/blob

   1 From 43f3f187e6f62ca40802afe39495c8a3e20b4bfa Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
   3 Date: Mon, 10 Jan 2022 01:50:50 +0100
   4 Subject: [PATCH] PCI: aardvark: Replace custom PCIE_CORE_INT_* macros with
   5  PCI_INTERRUPT_*
   6 MIME-Version: 1.0
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   9
  10 Header file linux/pci.h defines enum pci_interrupt_pin with corresponding
  11 PCI_INTERRUPT_* values.
  12
  13 Signed-off-by: Pali Rohár <pali@kernel.org>
  14 Signed-off-by: Marek Behún <kabel@kernel.org>
  15 ---
  16  drivers/pci/controller/pci-aardvark.c | 6 +-----
  17  1 file changed, 1 insertion(+), 5 deletions(-)
  18
  19 --- a/drivers/pci/controller/pci-aardvark.c
  20 +++ b/drivers/pci/controller/pci-aardvark.c
  21 @@ -38,10 +38,6 @@
  22  #define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN                        BIT(6)
  23  #define     PCIE_CORE_ERR_CAPCTL_ECRC_CHCK                     BIT(7)
  24  #define     PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV                 BIT(8)
  25 -#define     PCIE_CORE_INT_A_ASSERT_ENABLE                      1
  26 -#define     PCIE_CORE_INT_B_ASSERT_ENABLE                      2
  27 -#define     PCIE_CORE_INT_C_ASSERT_ENABLE                      3
  28 -#define     PCIE_CORE_INT_D_ASSERT_ENABLE                      4
  29  /* PIO registers base address and register offsets */
  30  #define PIO_BASE_ADDR                          0x4000
  31  #define PIO_CTRL                               (PIO_BASE_ADDR + 0x0)
  32 @@ -961,7 +957,7 @@ static int advk_sw_pci_bridge_init(struc
  33         bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
  34
  35         /* Support interrupt A for MSI feature */
  36 -       bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
  37 +       bridge->conf.intpin = PCI_INTERRUPT_INTA;
  38
  39         /* Aardvark HW provides PCIe Capability structure in version 2 */
  40         bridge->pcie_conf.cap = cpu_to_le16(2);