git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From 3105ff9d7111d15b686b8d14e8b4413a5c2a88ce Mon Sep 17 00:00:00 2001
   2 From: Lei Wei <quic_leiwei@quicinc.com>
   3 Date: Thu, 1 Feb 2024 13:03:14 +0800
   4 Subject: [PATCH 13/17] arm64: dts: qcom: ipq9574: Add PCS UNIPHY device tree
   5  support
   6
   7 The UNIPHY block in the IPQ SoC enables PCS/XPCS functions and helps in
   8 interfacing the Ethernet MAC to external PHYs.
   9
  10 There are three PCS UNIPHY instances available in the IPQ9574 SoC. The
  11 first UNIPHY has four PCS channels which can connect to QCA8075 Quad
  12 PHYs in QSGMII mode or QCA8085 PHYs with 10G-QXGMII mode. The second
  13 and third UNIPHYs each has one PCS channel which can connect with single
  14 10G capable PHY such as Aquantia 113c PHY in USXGMII mode.
  15
  16 Change-Id: I7832a71b12730d5bd7926a25f4feda371c09b58e
  17 Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
  18 ---
  19  arch/arm64/boot/dts/qcom/ipq9574.dtsi | 110 +++++++++++++++++++++++++-
  20  1 file changed, 109 insertions(+), 1 deletion(-)
  21
  22 diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
  23 index 02cf318e3d17..ce3a1b5d70ea 100644
  24 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
  25 +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
  26 @@ -3,7 +3,7 @@
  27   * IPQ9574 SoC device tree source
  28   *
  29   * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
  30 - * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  31 + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  32   */
  33
  34  #include <dt-bindings/clock/qcom,apss-ipq.h>
  35 @@ -776,6 +776,114 @@ frame@b128000 {
  36                         #power-domain-cells = <1>;
  37                         #interconnect-cells = <1>;
  38                 };
  39 +
  40 +               pcsuniphy0: ethernet-uniphy@7a00000 {
  41 +                       #address-cells = <1>;
  42 +                       #size-cells = <0>;
  43 +                       compatible = "qcom,ipq9574-uniphy";
  44 +                       reg = <0x7a00000 0x10000>;
  45 +                       clocks = <&gcc GCC_UNIPHY0_SYS_CLK>,
  46 +                                <&gcc GCC_UNIPHY0_AHB_CLK>;
  47 +                       clock-names = "sys",
  48 +                                     "ahb";
  49 +                       resets = <&gcc GCC_UNIPHY0_SYS_RESET>,
  50 +                                <&gcc GCC_UNIPHY0_AHB_RESET>,
  51 +                                <&gcc GCC_UNIPHY0_XPCS_RESET>;
  52 +                       reset-names = "sys",
  53 +                                     "ahb",
  54 +                                     "xpcs";
  55 +                       #clock-cells = <1>;
  56 +                       clock-output-names = "uniphy0_nss_rx_clk",
  57 +                                            "uniphy0_nss_tx_clk";
  58 +
  59 +                       pcsuniphy0_ch0: uniphy-ch@0 {
  60 +                               reg = <0>;
  61 +                               clocks = <&nsscc NSS_CC_UNIPHY_PORT1_RX_CLK>,
  62 +                                        <&nsscc NSS_CC_UNIPHY_PORT1_TX_CLK>;
  63 +                               clock-names = "ch_rx",
  64 +                                             "ch_tx";
  65 +                       };
  66 +
  67 +                       pcsuniphy0_ch1: uniphy-ch@1 {
  68 +                               reg = <1>;
  69 +                               clocks = <&nsscc NSS_CC_UNIPHY_PORT2_RX_CLK>,
  70 +                                        <&nsscc NSS_CC_UNIPHY_PORT2_TX_CLK>;
  71 +                               clock-names = "ch_rx",
  72 +                                             "ch_tx";
  73 +                       };
  74 +
  75 +                       pcsuniphy0_ch2: uniphy-ch@2 {
  76 +                               reg = <2>;
  77 +                               clocks = <&nsscc NSS_CC_UNIPHY_PORT3_RX_CLK>,
  78 +                                        <&nsscc NSS_CC_UNIPHY_PORT3_TX_CLK>;
  79 +                               clock-names = "ch_rx",
  80 +                                             "ch_tx";
  81 +                       };
  82 +
  83 +                       pcsuniphy0_ch3: uniphy-ch@3 {
  84 +                               reg = <3>;
  85 +                               clocks = <&nsscc NSS_CC_UNIPHY_PORT4_RX_CLK>,
  86 +                                        <&nsscc NSS_CC_UNIPHY_PORT4_TX_CLK>;
  87 +                               clock-names = "ch_rx",
  88 +                                             "ch_tx";
  89 +                       };
  90 +               };
  91 +
  92 +               pcsuniphy1: ethernet-uniphy@7a10000 {
  93 +                       #address-cells = <1>;
  94 +                       #size-cells = <0>;
  95 +                       compatible = "qcom,ipq9574-uniphy";
  96 +                       reg = <0x7a10000 0x10000>;
  97 +                       clocks = <&gcc GCC_UNIPHY1_SYS_CLK>,
  98 +                                <&gcc GCC_UNIPHY1_AHB_CLK>;
  99 +                       clock-names = "sys",
 100 +                                     "ahb";
 101 +                       resets = <&gcc GCC_UNIPHY1_SYS_RESET>,
 102 +                                <&gcc GCC_UNIPHY1_AHB_RESET>,
 103 +                                <&gcc GCC_UNIPHY1_XPCS_RESET>;
 104 +                       reset-names = "sys",
 105 +                                     "ahb",
 106 +                                     "xpcs";
 107 +                       #clock-cells = <1>;
 108 +                       clock-output-names = "uniphy1_nss_rx_clk",
 109 +                                            "uniphy1_nss_tx_clk";
 110 +
 111 +                       pcsuniphy1_ch0: uniphy-ch@0 {
 112 +                               reg = <0>;
 113 +                               clocks = <&nsscc NSS_CC_UNIPHY_PORT5_RX_CLK>,
 114 +                                        <&nsscc NSS_CC_UNIPHY_PORT5_TX_CLK>;
 115 +                               clock-names = "ch_rx",
 116 +                                             "ch_tx";
 117 +                       };
 118 +               };
 119 +
 120 +               pcsuniphy2: ethernet-uniphy@7a20000 {
 121 +                       #address-cells = <1>;
 122 +                       #size-cells = <0>;
 123 +                       compatible = "qcom,ipq9574-uniphy";
 124 +                       reg = <0x7a20000 0x10000>;
 125 +                       clocks = <&gcc GCC_UNIPHY2_SYS_CLK>,
 126 +                                <&gcc GCC_UNIPHY2_AHB_CLK>;
 127 +                       clock-names = "sys",
 128 +                                     "ahb";
 129 +                       resets = <&gcc GCC_UNIPHY2_SYS_RESET>,
 130 +                                <&gcc GCC_UNIPHY2_AHB_RESET>,
 131 +                                <&gcc GCC_UNIPHY2_XPCS_RESET>;
 132 +                       reset-names = "sys",
 133 +                                     "ahb",
 134 +                                     "xpcs";
 135 +                       #clock-cells = <1>;
 136 +                       clock-output-names = "uniphy2_nss_rx_clk",
 137 +                                            "uniphy2_nss_tx_clk";
 138 +
 139 +                       pcsuniphy2_ch0: uniphy-ch@0 {
 140 +                               reg = <0>;
 141 +                               clocks = <&nsscc NSS_CC_UNIPHY_PORT6_RX_CLK>,
 142 +                                        <&nsscc NSS_CC_UNIPHY_PORT6_TX_CLK>;
 143 +                               clock-names = "ch_rx",
 144 +                                             "ch_tx";
 145 +                       };
 146 +               };
 147         };
 148
 149         thermal-zones {
 150 --
 151 2.45.2
 152