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1 From 702a8f4744ed5b480f2b2411858184afdb10f9fd Mon Sep 17 00:00:00 2001
2 From: Matthew Hagan <mnhagan88@gmail.com>
3 Date: Fri, 6 Aug 2021 21:44:35 +0100
4 Subject: [PATCH] ARM: dts: NSP: Add DT files for Meraki MX65 series
5
6 MX65 & MX65W Hardware info:
7 - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz
8 - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR)
9 - Storage: 1 GB (Micron MT29F8G08ABACA)
10 - Networking: BCM58625 switch (2x 1GbE ports)
11 2x Qualcomm QCA8337 switches (10x 1GbE ports total)
12 - PSE: Broadcom BCM59111KMLG connected to LAN ports 11 & 12
13 - USB: 1x USB2.0
14 - Serial: Internal header
15 - WLAN(MX65W Only): 2x Broadcom BCM43520KMLG on the PCI bus.
16
17 Note that a driver and firmware image for the BCM59111 PSE has been
18 released under GPL, but this is not present in the kernel.
19
20 Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
21 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
22 ---
23 arch/arm/boot/dts/Makefile | 2 +
24 arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 279 ++++++++++++++++++
25 arch/arm/boot/dts/bcm958625-meraki-mx65.dts | 24 ++
26 arch/arm/boot/dts/bcm958625-meraki-mx65w.dts | 32 ++
27 4 files changed, 337 insertions(+)
28 create mode 100644 arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
29 create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65.dts
30 create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65w.dts
31
32 --- a/arch/arm/boot/dts/Makefile
33 +++ b/arch/arm/boot/dts/Makefile
34 @@ -161,6 +161,8 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \
35 bcm958625-meraki-mx64-a0.dtb \
36 bcm958625-meraki-mx64w.dtb \
37 bcm958625-meraki-mx64w-a0.dtb \
38 + bcm958625-meraki-mx65.dtb \
39 + bcm958625-meraki-mx65w.dtb \
40 bcm958625hr.dtb \
41 bcm988312hr.dtb \
42 bcm958625k.dtb
43 --- /dev/null
44 +++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
45 @@ -0,0 +1,279 @@
46 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
47 +/*
48 + * Device Tree Bindings for Cisco Meraki MX65 series (Alamo).
49 + *
50 + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
51 + */
52 +
53 +#include "bcm958625-meraki-mx6x-common.dtsi"
54 +
55 +/ {
56 + keys {
57 + compatible = "gpio-keys-polled";
58 + autorepeat;
59 + poll-interval = <20>;
60 +
61 + reset {
62 + label = "reset";
63 + linux,code = <KEY_RESTART>;
64 + gpios = <&gpioa 8 GPIO_ACTIVE_LOW>;
65 + };
66 + };
67 +
68 + leds {
69 + compatible = "gpio-leds";
70 +
71 + led-0 {
72 + /* green:wan1-left */
73 + function = LED_FUNCTION_ACTIVITY;
74 + function-enumerator = <0>;
75 + color = <LED_COLOR_ID_GREEN>;
76 + gpios = <&gpioa 25 GPIO_ACTIVE_LOW>;
77 + };
78 +
79 + led-1 {
80 + /* green:wan1-right */
81 + function = LED_FUNCTION_ACTIVITY;
82 + function-enumerator = <1>;
83 + color = <LED_COLOR_ID_GREEN>;
84 + gpios = <&gpioa 24 GPIO_ACTIVE_LOW>;
85 + };
86 +
87 + led-2 {
88 + /* green:wan2-left */
89 + function = LED_FUNCTION_ACTIVITY;
90 + function-enumerator = <2>;
91 + color = <LED_COLOR_ID_GREEN>;
92 + gpios = <&gpioa 27 GPIO_ACTIVE_LOW>;
93 + };
94 +
95 + led-3 {
96 + /* green:wan2-right */
97 + function = LED_FUNCTION_ACTIVITY;
98 + function-enumerator = <3>;
99 + color = <LED_COLOR_ID_GREEN>;
100 + gpios = <&gpioa 26 GPIO_ACTIVE_LOW>;
101 + };
102 +
103 + led-4 {
104 + /* amber:power */
105 + function = LED_FUNCTION_POWER;
106 + color = <LED_COLOR_ID_AMBER>;
107 + gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;
108 + default-state = "on";
109 + };
110 +
111 + led-5 {
112 + /* white:status */
113 + function = LED_FUNCTION_STATUS;
114 + color = <LED_COLOR_ID_WHITE>;
115 + gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;
116 + };
117 + };
118 +
119 + mdio-mii-mux {
120 + compatible = "mdio-mux-mmioreg";
121 + reg = <0x1803f1c0 0x4>;
122 + mux-mask = <0x2000>;
123 + mdio-parent-bus = <&mdio_ext>;
124 + #address-cells = <1>;
125 + #size-cells = <0>;
126 +
127 + mdio@0 {
128 + reg = <0x0>;
129 + #address-cells = <1>;
130 + #size-cells = <0>;
131 +
132 + phy_port6: phy@0 {
133 + reg = <0>;
134 + };
135 +
136 + phy_port7: phy@1 {
137 + reg = <1>;
138 + };
139 +
140 + phy_port8: phy@2 {
141 + reg = <2>;
142 + };
143 +
144 + phy_port9: phy@3 {
145 + reg = <3>;
146 + };
147 +
148 + phy_port10: phy@4 {
149 + reg = <4>;
150 + };
151 +
152 + switch@10 {
153 + compatible = "qca,qca8337";
154 + reg = <0x10>;
155 + dsa,member = <1 0>;
156 +
157 + ports {
158 + #address-cells = <1>;
159 + #size-cells = <0>;
160 + port@0 {
161 + reg = <0>;
162 + ethernet = <&sgmii1>;
163 + phy-mode = "sgmii";
164 + fixed-link {
165 + speed = <1000>;
166 + full-duplex;
167 + };
168 + };
169 +
170 + port@1 {
171 + reg = <1>;
172 + label = "lan8";
173 + phy-handle = <&phy_port6>;
174 + };
175 +
176 + port@2 {
177 + reg = <2>;
178 + label = "lan9";
179 + phy-handle = <&phy_port7>;
180 + };
181 +
182 + port@3 {
183 + reg = <3>;
184 + label = "lan10";
185 + phy-handle = <&phy_port8>;
186 + };
187 +
188 + port@4 {
189 + reg = <4>;
190 + label = "lan11";
191 + phy-handle = <&phy_port9>;
192 + };
193 +
194 + port@5 {
195 + reg = <5>;
196 + label = "lan12";
197 + phy-handle = <&phy_port10>;
198 + };
199 + };
200 + };
201 + };
202 +
203 + mdio-mii@2000 {
204 + reg = <0x2000>;
205 + #address-cells = <1>;
206 + #size-cells = <0>;
207 +
208 + phy_port1: phy@0 {
209 + reg = <0>;
210 + };
211 +
212 + phy_port2: phy@1 {
213 + reg = <1>;
214 + };
215 +
216 + phy_port3: phy@2 {
217 + reg = <2>;
218 + };
219 +
220 + phy_port4: phy@3 {
221 + reg = <3>;
222 + };
223 +
224 + phy_port5: phy@4 {
225 + reg = <4>;
226 + };
227 +
228 + switch@10 {
229 + compatible = "qca,qca8337";
230 + reg = <0x10>;
231 + dsa,member = <2 0>;
232 +
233 + ports {
234 + #address-cells = <1>;
235 + #size-cells = <0>;
236 + port@0 {
237 + reg = <0>;
238 + ethernet = <&sgmii0>;
239 + phy-mode = "sgmii";
240 + fixed-link {
241 + speed = <1000>;
242 + full-duplex;
243 + };
244 + };
245 +
246 + port@1 {
247 + reg = <1>;
248 + label = "lan3";
249 + phy-handle = <&phy_port1>;
250 + };
251 +
252 + port@2 {
253 + reg = <2>;
254 + label = "lan4";
255 + phy-handle = <&phy_port2>;
256 + };
257 +
258 + port@3 {
259 + reg = <3>;
260 + label = "lan5";
261 + phy-handle = <&phy_port3>;
262 + };
263 +
264 + port@4 {
265 + reg = <4>;
266 + label = "lan6";
267 + phy-handle = <&phy_port4>;
268 + };
269 +
270 + port@5 {
271 + reg = <5>;
272 + label = "lan7";
273 + phy-handle = <&phy_port5>;
274 + };
275 + };
276 + };
277 + };
278 + };
279 +};
280 +
281 +&srab {
282 + compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
283 + status = "okay";
284 + dsa,member = <0 0>;
285 +
286 + ports {
287 + port@0 {
288 + label = "wan1";
289 + reg = <0>;
290 + };
291 +
292 + port@1 {
293 + label = "wan2";
294 + reg = <1>;
295 + };
296 +
297 + sgmii0: port@4 {
298 + label = "sw0";
299 + reg = <4>;
300 + fixed-link {
301 + speed = <1000>;
302 + full-duplex;
303 + };
304 + };
305 +
306 + sgmii1: port@5 {
307 + label = "sw1";
308 + reg = <5>;
309 + fixed-link {
310 + speed = <1000>;
311 + full-duplex;
312 + };
313 + };
314 +
315 + port@8 {
316 + ethernet = <&amac2>;
317 + reg = <8>;
318 + fixed-link {
319 + speed = <1000>;
320 + full-duplex;
321 + };
322 + };
323 + };
324 +};
325 --- /dev/null
326 +++ b/arch/arm/boot/dts/bcm958625-meraki-mx65.dts
327 @@ -0,0 +1,24 @@
328 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
329 +/*
330 + * Device Tree Bindings for Cisco Meraki MX65.
331 + *
332 + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
333 + */
334 +
335 +/dts-v1/;
336 +
337 +#include "bcm958625-meraki-alamo.dtsi"
338 +
339 +/ {
340 + model = "Cisco Meraki MX65";
341 + compatible = "meraki,mx65", "brcm,bcm58625", "brcm,nsp";
342 +
343 + chosen {
344 + stdout-path = "serial0:115200n8";
345 + };
346 +
347 + memory@60000000 {
348 + device_type = "memory";
349 + reg = <0x60000000 0x80000000>;
350 + };
351 +};
352 --- /dev/null
353 +++ b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts
354 @@ -0,0 +1,32 @@
355 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
356 +/*
357 + * Device Tree Bindings for Cisco Meraki MX65W.
358 + *
359 + * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
360 + */
361 +
362 +/dts-v1/;
363 +
364 +#include "bcm958625-meraki-alamo.dtsi"
365 +
366 +/ {
367 + model = "Cisco Meraki MX65W";
368 + compatible = "meraki,mx65w", "brcm,bcm58625", "brcm,nsp";
369 +
370 + chosen {
371 + stdout-path = "serial0:115200n8";
372 + };
373 +
374 + memory@60000000 {
375 + device_type = "memory";
376 + reg = <0x60000000 0x80000000>;
377 + };
378 +};
379 +
380 +&pcie0 {
381 + status = "okay";
382 +};
383 +
384 +&pcie1 {
385 + status = "okay";
386 +};
Staging tree of Daniel Golle