git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From 0c994a28e7518f098c84a3049cb2915780db873a Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Fri, 14 May 2021 23:00:11 +0200
   4 Subject: [PATCH] devicetree: bindings: dsa: qca8k: Document internal mdio
   5  definition
   6
   7 Document new way of declare mapping of internal PHY to port.
   8 The new implementation directly declare the PHY connected to the port
   9 by adding a node in the switch node. The driver detect this and register
  10 an internal mdiobus using the mapping defined in the mdio node.
  11
  12 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  13 Reviewed-by: Rob Herring <robh@kernel.org>
  14 Signed-off-by: David S. Miller <davem@davemloft.net>
  15 ---
  16  .../devicetree/bindings/net/dsa/qca8k.txt     | 39 +++++++++++++++++++
  17  1 file changed, 39 insertions(+)
  18
  19 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
  20 +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
  21 @@ -21,6 +21,10 @@ described in dsa/dsa.txt. If the QCA8K s
  22  mdio-bus each subnode describing a port needs to have a valid phandle
  23  referencing the internal PHY it is connected to. This is because there's no
  24  N:N mapping of port and PHY id.
  25 +To declare the internal mdio-bus configuration, declare a mdio node in the
  26 +switch node and declare the phandle for the port referencing the internal
  27 +PHY is connected to. In this config a internal mdio-bus is registered and
  28 +the mdio MASTER is used as communication.
  29
  30  Don't use mixed external and internal mdio-bus configurations, as this is
  31  not supported by the hardware.
  32 @@ -150,26 +154,61 @@ for the internal master mdio-bus configu
  33                                 port@1 {
  34                                         reg = <1>;
  35                                         label = "lan1";
  36 +                                       phy-mode = "internal";
  37 +                                       phy-handle = <&phy_port1>;
  38                                 };
  39
  40                                 port@2 {
  41                                         reg = <2>;
  42                                         label = "lan2";
  43 +                                       phy-mode = "internal";
  44 +                                       phy-handle = <&phy_port2>;
  45                                 };
  46
  47                                 port@3 {
  48                                         reg = <3>;
  49                                         label = "lan3";
  50 +                                       phy-mode = "internal";
  51 +                                       phy-handle = <&phy_port3>;
  52                                 };
  53
  54                                 port@4 {
  55                                         reg = <4>;
  56                                         label = "lan4";
  57 +                                       phy-mode = "internal";
  58 +                                       phy-handle = <&phy_port4>;
  59                                 };
  60
  61                                 port@5 {
  62                                         reg = <5>;
  63                                         label = "wan";
  64 +                                       phy-mode = "internal";
  65 +                                       phy-handle = <&phy_port5>;
  66 +                               };
  67 +                       };
  68 +
  69 +                       mdio {
  70 +                               #address-cells = <1>;
  71 +                               #size-cells = <0>;
  72 +
  73 +                               phy_port1: phy@0 {
  74 +                                       reg = <0>;
  75 +                               };
  76 +
  77 +                               phy_port2: phy@1 {
  78 +                                       reg = <1>;
  79 +                               };
  80 +
  81 +                               phy_port3: phy@2 {
  82 +                                       reg = <2>;
  83 +                               };
  84 +
  85 +                               phy_port4: phy@3 {
  86 +                                       reg = <3>;
  87 +                               };
  88 +
  89 +                               phy_port5: phy@4 {
  90 +                                       reg = <4>;
  91                                 };
  92                         };
  93                 };