git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From 9e7eb0ea442ecb1c3fe443289e288694f10c5148 Mon Sep 17 00:00:00 2001
   2 From: Miquel Raynal <miquel.raynal@bootlin.com>
   3 Date: Thu, 27 Jan 2022 10:18:01 +0100
   4 Subject: [PATCH 07/15] spi: spi-mem: Add an ecc parameter to the spi_mem_op
   5  structure
   6
   7 Soon the SPI-NAND core will need a way to request a SPI controller to
   8 enable ECC support for a given operation. This is because of the
   9 pipelined integration of certain ECC engines, which are directly managed
  10 by the SPI controller itself.
  11
  12 Introduce a spi_mem_op additional field for this purpose: ecc.
  13
  14 So far this field is left unset and checked to be false by all
  15 the SPI controller drivers in their ->supports_op() hook, as they all
  16 call spi_mem_default_supports_op().
  17
  18 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
  19 Acked-by: Pratyush Yadav <p.yadav@ti.com>
  20 Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
  21 Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
  22 Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-7-miquel.raynal@bootlin.com
  23 (cherry picked from commit a433c2cbd75ab76f277364f44e76f32c7df306e7)
  24 ---
  25  drivers/spi/spi-mem.c       | 5 +++++
  26  include/linux/spi/spi-mem.h | 4 ++++
  27  2 files changed, 9 insertions(+)
  28
  29 --- a/drivers/spi/spi-mem.c
  30 +++ b/drivers/spi/spi-mem.c
  31 @@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct
  32                         return false;
  33         }
  34
  35 +       if (op->data.ecc) {
  36 +               if (!spi_mem_controller_is_capable(ctlr, ecc))
  37 +                       return false;
  38 +       }
  39 +
  40         return spi_mem_check_buswidth(mem, op);
  41  }
  42  EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
  43 --- a/include/linux/spi/spi-mem.h
  44 +++ b/include/linux/spi/spi-mem.h
  45 @@ -89,6 +89,7 @@ enum spi_mem_data_dir {
  46   * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
  47   * @data.buswidth: number of IO lanes used to send/receive the data
  48   * @data.dtr: whether the data should be sent in DTR mode or not
  49 + * @data.ecc: whether error correction is required or not
  50   * @data.dir: direction of the transfer
  51   * @data.nbytes: number of data bytes to send/receive. Can be zero if the
  52   *              operation does not involve transferring data
  53 @@ -119,6 +120,7 @@ struct spi_mem_op {
  54         struct {
  55                 u8 buswidth;
  56                 u8 dtr : 1;
  57 +               u8 ecc : 1;
  58                 enum spi_mem_data_dir dir;
  59                 unsigned int nbytes;
  60                 union {
  61 @@ -288,9 +290,11 @@ struct spi_controller_mem_ops {
  62  /**
  63   * struct spi_controller_mem_caps - SPI memory controller capabilities
  64   * @dtr: Supports DTR operations
  65 + * @ecc: Supports operations with error correction
  66   */
  67  struct spi_controller_mem_caps {
  68         bool dtr;
  69 +       bool ecc;
  70  };
  71
  72  #define spi_mem_controller_is_capable(ctlr, cap)       \