6d74a053e26db0a1df6b17b738dbefe0c35f8896
[openwrt/staging/ynezz.git] /
1 From 3f33626ac7037bd62df9391e899f50e076e58cf7 Mon Sep 17 00:00:00 2001
2 From: zachary <zhangzg@marvell.com>
3 Date: Wed, 25 Oct 2017 15:50:29 +0800
4 Subject: [PATCH] fix: clock: a3700: change pwm clock for 600/600 and 1200/750
5 preset
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 This patch is to change pwm clock from 100MHz to 50MHz for 600/600 and
11 1200/750 preset to align with other presets.
12
13 Change-Id: I067e189043be8c776bd3e7015a06f8ddf2590b96
14 Signed-off-by: zachary <zhangzg@marvell.com>
15 Reviewed-on: http://vgitil04.il.marvell.com:8080/45513
16 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
17 Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
18 Reviewed-by: Hua Jing <jinghua@marvell.com>
19 Signed-off-by: Marek BehĂșn <marek.behun@nic.cz>
20 ---
21 wtmi/clock.c | 4 ++--
22 1 file changed, 2 insertions(+), 2 deletions(-)
23
24 diff --git a/wtmi/clock.c b/wtmi/clock.c
25 index 97c2825..1a1f0c6 100644
26 --- a/wtmi/clock.c
27 +++ b/wtmi/clock.c
28 @@ -447,7 +447,7 @@ static struct clock_cfg clk_cfg_all[] = {\
29 /* NorthBridge */\
30 {{TBG_A_S, TBG_B_S, TBG_B_S, TBG_B_S, TBG_A_P, TBG_A_P, TBG_A_P,\
31 TBG_B_S, TBG_B_S, TBG_A_P, TBG_B_S, TBG_A_P, TBG_B_S},\
32 - {2, 5, 2, 4, 1, 2, 6, 2}, /* DIV0 */\
33 + {4, 5, 2, 4, 1, 2, 6, 2}, /* DIV0 */\
34 {1, 5, 2, 5, 2, 3, 2, 2, 3}, /* DIV1 */\
35 {4, 1, 5, 1, 3, 1, 2, 0, 0, 1} }, /* DIV2 */\
36 /* SouthBridge */\
37 @@ -495,7 +495,7 @@ static struct clock_cfg clk_cfg_all[] = {\
38 /* NorthBridge */\
39 {{TBG_B_S, TBG_B_S, TBG_B_S, TBG_B_S, TBG_B_S, TBG_B_S, TBG_B_S,\
40 TBG_B_S, TBG_A_S, TBG_B_S, TBG_A_P, TBG_B_S, TBG_A_S},\
41 - {3, 4, 3, 4, 1, 1, 5, 1}, /* DIV0 */\
42 + {6, 4, 3, 4, 1, 1, 5, 1}, /* DIV0 */\
43 {1, 6, 3, 4, 1, 6, 1, 1, 6}, /* DIV1 */\
44 {4, 1, 6, 1, 3, 1, 3, 0, 0, 1} }, /* DIV2 */\
45 /* SouthBridge */\
46 --
47 2.30.2
48