6bb45ccb1fd8f0db2bf0602625161f2f1437c27d
[openwrt/staging/blogic.git] /
1 From 39192141aa16809323c24d8910e3a63488f7f55d Mon Sep 17 00:00:00 2001
2 From: Marek Szyprowski <m.szyprowski@samsung.com>
3 Date: Thu, 27 Feb 2020 12:51:46 +0100
4 Subject: [PATCH] PCI: brcmstb: Fix build on 32bit ARM platforms with
5 older compilers
6
7 commit 73a7a271b3eee7b83f29b13866163776f1cbef89 upstream.
8
9 Some older compilers have no implementation for the helper for 64-bit
10 unsigned division/modulo, so linking pcie-brcmstb driver causes the
11 "undefined reference to `__aeabi_uldivmod'" error.
12
13 *rc_bar2_size is always a power of two, because it is calculated as:
14 "1ULL << fls64(entry->res->end - entry->res->start)", so the modulo
15 operation in the subsequent check can be replaced by a simple logical
16 AND with a proper mask.
17
18 Link: https://lore.kernel.org/r/20200227115146.24515-1-m.szyprowski@samsung.com
19 Fixes: c0452137034b ("PCI: brcmstb: Add Broadcom STB PCIe host controller driver")
20 Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
21 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
22 Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
23 Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
24 ---
25 drivers/pci/controller/pcie-brcmstb.c | 2 +-
26 1 file changed, 1 insertion(+), 1 deletion(-)
27
28 --- a/drivers/pci/controller/pcie-brcmstb.c
29 +++ b/drivers/pci/controller/pcie-brcmstb.c
30 @@ -670,7 +670,7 @@ static inline int brcm_pcie_get_rc_bar2_
31 * outbound memory @ 3GB). So instead it will start at the 1x
32 * multiple of its size
33 */
34 - if (!*rc_bar2_size || *rc_bar2_offset % *rc_bar2_size ||
35 + if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) ||
36 (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
37 dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n",
38 *rc_bar2_size, *rc_bar2_offset);