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1 From: Chuanjia Liu <chuanjia.liu@mediatek.com>
2 Date: Mon, 23 Aug 2021 11:27:59 +0800
3 Subject: [PATCH] arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622
4
5 There are two independent PCIe controllers in MT2712 and MT7622
6 platform. Each of them should contain an independent MSI domain.
7
8 In old dts architecture, MSI domain will be inherited from the root
9 bridge, and all of the devices will share the same MSI domain.
10 Hence that, the PCIe devices will not work properly if the irq number
11 which required is more than 32.
12
13 Split the PCIe node for MT2712 and MT7622 platform to comply with
14 the hardware design and fix MSI issue.
15
16 Signed-off-by: Chuanjia Liu <chuanjia.liu@mediatek.com>
17 Acked-by: Ryder Lee <ryder.lee@mediatek.com>
18 Link: https://lore.kernel.org/r/20210823032800.1660-6-chuanjia.liu@mediatek.com
19 Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
20 ---
21
22 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
23 +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
24 @@ -915,64 +915,67 @@
25 };
26 };
27
28 - pcie: pcie@11700000 {
29 + pcie1: pcie@112ff000 {
30 compatible = "mediatek,mt2712-pcie";
31 device_type = "pci";
32 - reg = <0 0x11700000 0 0x1000>,
33 - <0 0x112ff000 0 0x1000>;
34 - reg-names = "port0", "port1";
35 + reg = <0 0x112ff000 0 0x1000>;
36 + reg-names = "port1";
37 + linux,pci-domain = <1>;
38 #address-cells = <3>;
39 #size-cells = <2>;
40 - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
41 - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
42 - clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
43 - <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
44 - <&pericfg CLK_PERI_PCIE0>,
45 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
46 + interrupt-names = "pcie_irq";
47 + clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
48 <&pericfg CLK_PERI_PCIE1>;
49 - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
50 - phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
51 - phy-names = "pcie-phy0", "pcie-phy1";
52 + clock-names = "sys_ck1", "ahb_ck1";
53 + phys = <&u3port1 PHY_TYPE_PCIE>;
54 + phy-names = "pcie-phy1";
55 bus-range = <0x00 0xff>;
56 - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
57 + ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
58 + status = "disabled";
59
60 - pcie0: pcie@0,0 {
61 - device_type = "pci";
62 - status = "disabled";
63 - reg = <0x0000 0 0 0 0>;
64 - #address-cells = <3>;
65 - #size-cells = <2>;
66 + #interrupt-cells = <1>;
67 + interrupt-map-mask = <0 0 0 7>;
68 + interrupt-map = <0 0 0 1 &pcie_intc1 0>,
69 + <0 0 0 2 &pcie_intc1 1>,
70 + <0 0 0 3 &pcie_intc1 2>,
71 + <0 0 0 4 &pcie_intc1 3>;
72 + pcie_intc1: interrupt-controller {
73 + interrupt-controller;
74 + #address-cells = <0>;
75 #interrupt-cells = <1>;
76 - ranges;
77 - interrupt-map-mask = <0 0 0 7>;
78 - interrupt-map = <0 0 0 1 &pcie_intc0 0>,
79 - <0 0 0 2 &pcie_intc0 1>,
80 - <0 0 0 3 &pcie_intc0 2>,
81 - <0 0 0 4 &pcie_intc0 3>;
82 - pcie_intc0: interrupt-controller {
83 - interrupt-controller;
84 - #address-cells = <0>;
85 - #interrupt-cells = <1>;
86 - };
87 };
88 + };
89 +
90 + pcie0: pcie@11700000 {
91 + compatible = "mediatek,mt2712-pcie";
92 + device_type = "pci";
93 + reg = <0 0x11700000 0 0x1000>;
94 + reg-names = "port0";
95 + linux,pci-domain = <0>;
96 + #address-cells = <3>;
97 + #size-cells = <2>;
98 + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
99 + interrupt-names = "pcie_irq";
100 + clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
101 + <&pericfg CLK_PERI_PCIE0>;
102 + clock-names = "sys_ck0", "ahb_ck0";
103 + phys = <&u3port0 PHY_TYPE_PCIE>;
104 + phy-names = "pcie-phy0";
105 + bus-range = <0x00 0xff>;
106 + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
107 + status = "disabled";
108
109 - pcie1: pcie@1,0 {
110 - device_type = "pci";
111 - status = "disabled";
112 - reg = <0x0800 0 0 0 0>;
113 - #address-cells = <3>;
114 - #size-cells = <2>;
115 + #interrupt-cells = <1>;
116 + interrupt-map-mask = <0 0 0 7>;
117 + interrupt-map = <0 0 0 1 &pcie_intc0 0>,
118 + <0 0 0 2 &pcie_intc0 1>,
119 + <0 0 0 3 &pcie_intc0 2>,
120 + <0 0 0 4 &pcie_intc0 3>;
121 + pcie_intc0: interrupt-controller {
122 + interrupt-controller;
123 + #address-cells = <0>;
124 #interrupt-cells = <1>;
125 - ranges;
126 - interrupt-map-mask = <0 0 0 7>;
127 - interrupt-map = <0 0 0 1 &pcie_intc1 0>,
128 - <0 0 0 2 &pcie_intc1 1>,
129 - <0 0 0 3 &pcie_intc1 2>,
130 - <0 0 0 4 &pcie_intc1 3>;
131 - pcie_intc1: interrupt-controller {
132 - interrupt-controller;
133 - #address-cells = <0>;
134 - #interrupt-cells = <1>;
135 - };
136 };
137 };
138
139 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
140 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
141 @@ -302,18 +302,16 @@
142 };
143 };
144
145 -&pcie {
146 +&pcie0 {
147 pinctrl-names = "default";
148 - pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
149 + pinctrl-0 = <&pcie0_pins>;
150 status = "okay";
151 +};
152
153 - pcie@0,0 {
154 - status = "okay";
155 - };
156 -
157 - pcie@1,0 {
158 - status = "okay";
159 - };
160 +&pcie1 {
161 + pinctrl-names = "default";
162 + pinctrl-0 = <&pcie1_pins>;
163 + status = "okay";
164 };
165
166 &pio {
167 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
168 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
169 @@ -232,18 +232,16 @@
170 };
171 };
172
173 -&pcie {
174 +&pcie0 {
175 pinctrl-names = "default";
176 - pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
177 + pinctrl-0 = <&pcie0_pins>;
178 status = "okay";
179 +};
180
181 - pcie@0,0 {
182 - status = "okay";
183 - };
184 -
185 - pcie@1,0 {
186 - status = "okay";
187 - };
188 +&pcie1 {
189 + pinctrl-names = "default";
190 + pinctrl-0 = <&pcie1_pins>;
191 + status = "okay";
192 };
193
194 &pio {
195 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
196 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
197 @@ -809,75 +809,83 @@
198 #reset-cells = <1>;
199 };
200
201 - pcie: pcie@1a140000 {
202 + pciecfg: pciecfg@1a140000 {
203 + compatible = "mediatek,generic-pciecfg", "syscon";
204 + reg = <0 0x1a140000 0 0x1000>;
205 + };
206 +
207 + pcie0: pcie@1a143000 {
208 compatible = "mediatek,mt7622-pcie";
209 device_type = "pci";
210 - reg = <0 0x1a140000 0 0x1000>,
211 - <0 0x1a143000 0 0x1000>,
212 - <0 0x1a145000 0 0x1000>;
213 - reg-names = "subsys", "port0", "port1";
214 + reg = <0 0x1a143000 0 0x1000>;
215 + reg-names = "port0";
216 + linux,pci-domain = <0>;
217 #address-cells = <3>;
218 #size-cells = <2>;
219 - interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
220 - <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
221 + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
222 + interrupt-names = "pcie_irq";
223 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
224 - <&pciesys CLK_PCIE_P1_MAC_EN>,
225 - <&pciesys CLK_PCIE_P0_AHB_EN>,
226 <&pciesys CLK_PCIE_P0_AHB_EN>,
227 <&pciesys CLK_PCIE_P0_AUX_EN>,
228 - <&pciesys CLK_PCIE_P1_AUX_EN>,
229 <&pciesys CLK_PCIE_P0_AXI_EN>,
230 - <&pciesys CLK_PCIE_P1_AXI_EN>,
231 <&pciesys CLK_PCIE_P0_OBFF_EN>,
232 - <&pciesys CLK_PCIE_P1_OBFF_EN>,
233 - <&pciesys CLK_PCIE_P0_PIPE_EN>,
234 - <&pciesys CLK_PCIE_P1_PIPE_EN>;
235 - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
236 - "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
237 - "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
238 + <&pciesys CLK_PCIE_P0_PIPE_EN>;
239 + clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
240 + "axi_ck0", "obff_ck0", "pipe_ck0";
241 +
242 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
243 bus-range = <0x00 0xff>;
244 - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
245 + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
246 status = "disabled";
247
248 - pcie0: pcie@0,0 {
249 - reg = <0x0000 0 0 0 0>;
250 - #address-cells = <3>;
251 - #size-cells = <2>;
252 + #interrupt-cells = <1>;
253 + interrupt-map-mask = <0 0 0 7>;
254 + interrupt-map = <0 0 0 1 &pcie_intc0 0>,
255 + <0 0 0 2 &pcie_intc0 1>,
256 + <0 0 0 3 &pcie_intc0 2>,
257 + <0 0 0 4 &pcie_intc0 3>;
258 + pcie_intc0: interrupt-controller {
259 + interrupt-controller;
260 + #address-cells = <0>;
261 #interrupt-cells = <1>;
262 - ranges;
263 - status = "disabled";
264 -
265 - interrupt-map-mask = <0 0 0 7>;
266 - interrupt-map = <0 0 0 1 &pcie_intc0 0>,
267 - <0 0 0 2 &pcie_intc0 1>,
268 - <0 0 0 3 &pcie_intc0 2>,
269 - <0 0 0 4 &pcie_intc0 3>;
270 - pcie_intc0: interrupt-controller {
271 - interrupt-controller;
272 - #address-cells = <0>;
273 - #interrupt-cells = <1>;
274 - };
275 };
276 + };
277
278 - pcie1: pcie@1,0 {
279 - reg = <0x0800 0 0 0 0>;
280 - #address-cells = <3>;
281 - #size-cells = <2>;
282 - #interrupt-cells = <1>;
283 - ranges;
284 - status = "disabled";
285 + pcie1: pcie@1a145000 {
286 + compatible = "mediatek,mt7622-pcie";
287 + device_type = "pci";
288 + reg = <0 0x1a145000 0 0x1000>;
289 + reg-names = "port1";
290 + linux,pci-domain = <1>;
291 + #address-cells = <3>;
292 + #size-cells = <2>;
293 + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
294 + interrupt-names = "pcie_irq";
295 + clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
296 + /* designer has connect RC1 with p0_ahb clock */
297 + <&pciesys CLK_PCIE_P0_AHB_EN>,
298 + <&pciesys CLK_PCIE_P1_AUX_EN>,
299 + <&pciesys CLK_PCIE_P1_AXI_EN>,
300 + <&pciesys CLK_PCIE_P1_OBFF_EN>,
301 + <&pciesys CLK_PCIE_P1_PIPE_EN>;
302 + clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
303 + "axi_ck1", "obff_ck1", "pipe_ck1";
304 +
305 + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
306 + bus-range = <0x00 0xff>;
307 + ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
308 + status = "disabled";
309
310 - interrupt-map-mask = <0 0 0 7>;
311 - interrupt-map = <0 0 0 1 &pcie_intc1 0>,
312 - <0 0 0 2 &pcie_intc1 1>,
313 - <0 0 0 3 &pcie_intc1 2>,
314 - <0 0 0 4 &pcie_intc1 3>;
315 - pcie_intc1: interrupt-controller {
316 - interrupt-controller;
317 - #address-cells = <0>;
318 - #interrupt-cells = <1>;
319 - };
320 + #interrupt-cells = <1>;
321 + interrupt-map-mask = <0 0 0 7>;
322 + interrupt-map = <0 0 0 1 &pcie_intc1 0>,
323 + <0 0 0 2 &pcie_intc1 1>,
324 + <0 0 0 3 &pcie_intc1 2>,
325 + <0 0 0 4 &pcie_intc1 3>;
326 + pcie_intc1: interrupt-controller {
327 + interrupt-controller;
328 + #address-cells = <0>;
329 + #interrupt-cells = <1>;
330 };
331 };
332
Staging tree of Jo-Philipp Wich