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1 From cca74bed37af1c8217bcd8282d9b384efdbf73bd Mon Sep 17 00:00:00 2001
2 From: Shiji Yang <yangshiji66@outlook.com>
3 Date: Thu, 19 Oct 2023 19:58:58 +0800
4 Subject: wifi: rt2x00: rework MT7620 PA/LNA RF calibration
5
6 1. Move MT7620 PA/LNA calibration code to dedicated functions.
7 2. For external PA/LNA devices, restore RF and BBP registers before
8 R-Calibration.
9 3. Do Rx DCOC calibration again before RXIQ calibration.
10 4. Add some missing LNA related registers' initialization.
11
12 Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
13 Acked-by: Stanislaw Gruszka <stf_xl@wp.pl>
14 Signed-off-by: Kalle Valo <kvalo@kernel.org>
15 Link: https://lore.kernel.org/r/TYAP286MB0315979F92DC563019B8F238BCD4A@TYAP286MB0315.JPNP286.PROD.OUTLOOK.COM
16 ---
17 drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 176 +++++++++++++++++--------
18 drivers/net/wireless/ralink/rt2x00/rt2x00.h | 6 +
19 2 files changed, 130 insertions(+), 52 deletions(-)
20
21 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
22 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
23 @@ -4468,41 +4468,6 @@ static void rt2800_config_channel(struct
24 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
25
26 usleep_range(1000, 1500);
27 -
28 - if (test_bit(CAPABILITY_EXTERNAL_PA_TX0,
29 - &rt2x00dev->cap_flags)) {
30 - reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
31 - reg |= 0x00000101;
32 - rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
33 -
34 - reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
35 - reg |= 0x00000101;
36 - rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
37 -
38 - rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73);
39 - rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73);
40 - rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73);
41 - rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
42 - rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xC8);
43 - rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xA4);
44 - rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05);
45 - rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
46 - rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xC8);
47 - rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xA4);
48 - rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05);
49 - rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
50 - rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xC8);
51 - rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xA4);
52 - rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05);
53 - rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00);
54 -
55 - rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
56 - 0x36303636);
57 - rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,
58 - 0x6C6C6B6C);
59 - rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,
60 - 0x6C6C6B6C);
61 - }
62 }
63
64 bbp = rt2800_bbp_read(rt2x00dev, 4);
65 @@ -5612,16 +5577,6 @@ void rt2800_vco_calibration(struct rt2x0
66 }
67 }
68 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
69 -
70 - if (rt2x00_rt(rt2x00dev, RT6352)) {
71 - if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
72 - rt2800_bbp_write(rt2x00dev, 75, 0x68);
73 - rt2800_bbp_write(rt2x00dev, 76, 0x4C);
74 - rt2800_bbp_write(rt2x00dev, 79, 0x1C);
75 - rt2800_bbp_write(rt2x00dev, 80, 0x0C);
76 - rt2800_bbp_write(rt2x00dev, 82, 0xB6);
77 - }
78 - }
79 }
80 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
81
82 @@ -10348,6 +10303,128 @@ do_cal:
83 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
84 }
85
86 +static void rt2800_restore_rf_bbp_rt6352(struct rt2x00_dev *rt2x00dev)
87 +{
88 + if (rt2x00_has_cap_external_pa(rt2x00dev)) {
89 + rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0);
90 + rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0);
91 + }
92 +
93 + if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
94 + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
95 + rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
96 + rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
97 + }
98 +
99 + if (rt2x00_has_cap_external_pa(rt2x00dev)) {
100 + rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xd3);
101 + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xb3);
102 + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xd5);
103 + rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
104 + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6c);
105 + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xfc);
106 + rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1f);
107 + rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
108 + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
109 + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xff);
110 + rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1c);
111 + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
112 + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6b);
113 + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xf7);
114 + rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
115 + }
116 +
117 + if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
118 + rt2800_bbp_write(rt2x00dev, 75, 0x60);
119 + rt2800_bbp_write(rt2x00dev, 76, 0x44);
120 + rt2800_bbp_write(rt2x00dev, 79, 0x1c);
121 + rt2800_bbp_write(rt2x00dev, 80, 0x0c);
122 + rt2800_bbp_write(rt2x00dev, 82, 0xB6);
123 + }
124 +
125 + if (rt2x00_has_cap_external_pa(rt2x00dev)) {
126 + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x3630363a);
127 + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6c6c666c);
128 + rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6c6c666c);
129 + }
130 +}
131 +
132 +static void rt2800_calibration_rt6352(struct rt2x00_dev *rt2x00dev)
133 +{
134 + u32 reg;
135 +
136 + if (rt2x00_has_cap_external_pa(rt2x00dev) ||
137 + rt2x00_has_cap_external_lna_bg(rt2x00dev))
138 + rt2800_restore_rf_bbp_rt6352(rt2x00dev);
139 +
140 + rt2800_r_calibration(rt2x00dev);
141 + rt2800_rf_self_txdc_cal(rt2x00dev);
142 + rt2800_rxdcoc_calibration(rt2x00dev);
143 + rt2800_bw_filter_calibration(rt2x00dev, true);
144 + rt2800_bw_filter_calibration(rt2x00dev, false);
145 + rt2800_loft_iq_calibration(rt2x00dev);
146 +
147 + /* missing DPD calibration for internal PA devices */
148 +
149 + rt2800_rxdcoc_calibration(rt2x00dev);
150 + rt2800_rxiq_calibration(rt2x00dev);
151 +
152 + if (!rt2x00_has_cap_external_pa(rt2x00dev) &&
153 + !rt2x00_has_cap_external_lna_bg(rt2x00dev))
154 + return;
155 +
156 + if (rt2x00_has_cap_external_pa(rt2x00dev)) {
157 + reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
158 + reg |= 0x00000101;
159 + rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
160 +
161 + reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
162 + reg |= 0x00000101;
163 + rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
164 + }
165 +
166 + if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
167 + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66);
168 + rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20);
169 + rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x42);
170 + }
171 +
172 + if (rt2x00_has_cap_external_pa(rt2x00dev)) {
173 + rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73);
174 + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73);
175 + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73);
176 + rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
177 + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xc8);
178 + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xa4);
179 + rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05);
180 + rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
181 + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xc8);
182 + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xa4);
183 + rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05);
184 + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
185 + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xc8);
186 + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xa4);
187 + rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05);
188 + }
189 +
190 + if (rt2x00_has_cap_external_pa(rt2x00dev))
191 + rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00);
192 +
193 + if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
194 + rt2800_bbp_write(rt2x00dev, 75, 0x68);
195 + rt2800_bbp_write(rt2x00dev, 76, 0x4c);
196 + rt2800_bbp_write(rt2x00dev, 79, 0x1c);
197 + rt2800_bbp_write(rt2x00dev, 80, 0x0c);
198 + rt2800_bbp_write(rt2x00dev, 82, 0xb6);
199 + }
200 +
201 + if (rt2x00_has_cap_external_pa(rt2x00dev)) {
202 + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x36303636);
203 + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6c6c6b6c);
204 + rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6c6c6b6c);
205 + }
206 +}
207 +
208 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
209 {
210 /* Initialize RF central register to default value */
211 @@ -10612,13 +10689,8 @@ static void rt2800_init_rfcsr_6352(struc
212 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
213 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
214
215 - rt2800_r_calibration(rt2x00dev);
216 - rt2800_rf_self_txdc_cal(rt2x00dev);
217 - rt2800_rxdcoc_calibration(rt2x00dev);
218 - rt2800_bw_filter_calibration(rt2x00dev, true);
219 - rt2800_bw_filter_calibration(rt2x00dev, false);
220 - rt2800_loft_iq_calibration(rt2x00dev);
221 - rt2800_rxiq_calibration(rt2x00dev);
222 + /* Do calibration and init PA/LNA */
223 + rt2800_calibration_rt6352(rt2x00dev);
224 }
225
226 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
227 --- a/drivers/net/wireless/ralink/rt2x00/rt2x00.h
228 +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00.h
229 @@ -1263,6 +1263,12 @@ rt2x00_has_cap_external_lna_bg(struct rt
230 }
231
232 static inline bool
233 +rt2x00_has_cap_external_pa(struct rt2x00_dev *rt2x00dev)
234 +{
235 + return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_EXTERNAL_PA_TX0);
236 +}
237 +
238 +static inline bool
239 rt2x00_has_cap_double_antenna(struct rt2x00_dev *rt2x00dev)
240 {
241 return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_DOUBLE_ANTENNA);
Staging tree of Piotr Dymacz