git.openwrt.org Git - openwrt/staging/noltari.git/blob

   1 From cb1acabb459677efbf95c54ce1dc5252be30a018 Mon Sep 17 00:00:00 2001
   2 From: Jim Quinlan <jim2101024@gmail.com>
   3 Date: Mon, 15 Jan 2018 18:28:39 -0500
   4 Subject: [PATCH] dt-bindings: pci: Add DT docs for Brcmstb PCIe device
   5
   6 The DT bindings description of the Brcmstb PCIe device is described.  This
   7 node can be used by almost all Broadcom settop box chips, using
   8 ARM, ARM64, or MIPS CPU architectures.
   9
  10 Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
  11 ---
  12  .../devicetree/bindings/pci/brcmstb-pcie.txt  | 59 +++++++++++++++++++
  13  1 file changed, 59 insertions(+)
  14  create mode 100644 Documentation/devicetree/bindings/pci/brcmstb-pcie.txt
  15
  16 --- /dev/null
  17 +++ b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt
  18 @@ -0,0 +1,59 @@
  19 +Brcmstb PCIe Host Controller Device Tree Bindings
  20 +
  21 +Required Properties:
  22 +- compatible
  23 +  "brcm,bcm7425-pcie" -- for 7425 family MIPS-based SOCs.
  24 +  "brcm,bcm7435-pcie" -- for 7435 family MIPS-based SOCs.
  25 +  "brcm,bcm7445-pcie" -- for 7445 and later ARM based SOCs (not including
  26 +      the 7278).
  27 +  "brcm,bcm7278-pcie"  -- for 7278 family ARM-based SOCs.
  28 +
  29 +- reg -- the register start address and length for the PCIe reg block.
  30 +- interrupts -- two interrupts are specified; the first interrupt is for
  31 +     the PCI host controller and the second is for MSI if the built-in
  32 +     MSI controller is to be used.
  33 +- interrupt-names -- names of the interrupts (above): "pcie" and "msi".
  34 +- #address-cells -- set to <3>.
  35 +- #size-cells -- set to <2>.
  36 +- #interrupt-cells: set to <1>.
  37 +- interrupt-map-mask and interrupt-map, standard PCI properties to define the
  38 +     mapping of the PCIe interface to interrupt numbers.
  39 +- ranges: ranges for the PCI memory and I/O regions.
  40 +- linux,pci-domain -- should be unique per host controller.
  41 +
  42 +Optional Properties:
  43 +- clocks -- phandle of pcie clock.
  44 +- clock-names -- set to "sw_pcie" if clocks is used.
  45 +- dma-ranges -- Specifies the inbound memory mapping regions when
  46 +     an "identity map" is not possible.
  47 +- msi-controller -- this property is typically specified to have the
  48 +     PCIe controller use its internal MSI controller.
  49 +- msi-parent -- set to use an external MSI interrupt controller.
  50 +- brcm,enable-ssc -- (boolean) indicates usage of spread-spectrum clocking.
  51 +- max-link-speed --  (integer) indicates desired generation of link:
  52 +     1 => 2.5 Gbps (gen1), 2 => 5.0 Gbps (gen2), 3 => 8.0 Gbps (gen3).
  53 +
  54 +Example Node:
  55 +
  56 +pcie0: pcie@f0460000 {
  57 +               reg = <0x0 0xf0460000 0x0 0x9310>;
  58 +               interrupts = <0x0 0x0 0x4>;
  59 +               compatible = "brcm,bcm7445-pcie";
  60 +               #address-cells = <3>;
  61 +               #size-cells = <2>;
  62 +               ranges = <0x02000000 0x00000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x08000000
  63 +                         0x02000000 0x00000000 0x08000000 0x00000000 0xc8000000 0x00000000 0x08000000>;
  64 +               #interrupt-cells = <1>;
  65 +               interrupt-map-mask = <0 0 0 7>;
  66 +               interrupt-map = <0 0 0 1 &intc 0 47 3
  67 +                                0 0 0 2 &intc 0 48 3
  68 +                                0 0 0 3 &intc 0 49 3
  69 +                                0 0 0 4 &intc 0 50 3>;
  70 +               clocks = <&sw_pcie0>;
  71 +               clock-names = "sw_pcie";
  72 +               msi-parent = <&pcie0>;  /* use PCIe's internal MSI controller */
  73 +               msi-controller;         /* use PCIe's internal MSI controller */
  74 +               brcm,ssc;
  75 +               max-link-speed = <1>;
  76 +               linux,pci-domain = <0>;
  77 +       };