git.openwrt.org Git - openwrt/staging/wigyori.git/blob

   1 From 7e64c4e922cddea72dacd3f0d8f395d9182ea5bc Mon Sep 17 00:00:00 2001
   2 From: Wen He <wen.he_1@nxp.com>
   3 Date: Mon, 14 Oct 2019 15:13:27 +0800
   4 Subject: [PATCH] arm64: dts: ls1028a: Update #clock-cells of dpclk node
   5
   6 Update the property #clock-cells = <1> to #clock-cells = <0> of the
   7 dpclk, since the Display output pixel clock driver provides single
   8 clock output.
   9
  10 Signed-off-by: Wen He <wen.he_1@nxp.com>
  11 Signed-off-by: Shawn Guo <shawnguo@kernel.org>
  12 ---
  13  arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 4 ++--
  14  1 file changed, 2 insertions(+), 2 deletions(-)
  15
  16 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
  17 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
  18 @@ -86,7 +86,7 @@
  19         dpclk: clock-controller@f1f0000 {
  20                 compatible = "fsl,ls1028a-plldig";
  21                 reg = <0x0 0xf1f0000 0x0 0xffff>;
  22 -               #clock-cells = <1>;
  23 +               #clock-cells = <0>;
  24                 clocks = <&osc_27m>;
  25         };
  26
  27 @@ -866,7 +866,7 @@
  28                 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
  29                              <0 223 IRQ_TYPE_LEVEL_HIGH>;
  30                 interrupt-names = "DE", "SE";
  31 -               clocks = <&dpclk 0>, <&clockgen 2 2>, <&clockgen 2 2>,
  32 +               clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>,
  33                          <&clockgen 2 2>;
  34                 clock-names = "pxlclk", "mclk", "aclk", "pclk";
  35                 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;