git.openwrt.org Git - openwrt/staging/wigyori.git/blob

   1 From 731d613338ec6de482053ffa3f71be2325b0f8eb Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Thu, 14 Oct 2021 00:39:09 +0200
   4 Subject: dt-bindings: net: dsa: qca8k: Document support for CPU port 6
   5
   6 The switch now support CPU port to be set 6 instead of be hardcoded to
   7 0. Document support for it and describe logic selection.
   8
   9 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  10 Signed-off-by: David S. Miller <davem@davemloft.net>
  11 ---
  12  Documentation/devicetree/bindings/net/dsa/qca8k.txt | 6 +++++-
  13  1 file changed, 5 insertions(+), 1 deletion(-)
  14
  15 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
  16 +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
  17 @@ -29,7 +29,11 @@ the mdio MASTER is used as communication
  18  Don't use mixed external and internal mdio-bus configurations, as this is
  19  not supported by the hardware.
  20
  21 -The CPU port of this switch is always port 0.
  22 +This switch support 2 CPU port. Normally and advised configuration is with
  23 +CPU port set to port 0. It is also possible to set the CPU port to port 6
  24 +if the device requires it. The driver will configure the switch to the defined
  25 +port. With both CPU port declared the first CPU port is selected as primary
  26 +and the secondary CPU ignored.
  27
  28  A CPU port node has the following optional node:
  29