git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From 3027d89f87707e7f3e5b683e0d37a32afb5bde96 Mon Sep 17 00:00:00 2001
   2 From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
   3 Date: Thu, 27 Oct 2022 14:11:23 +0100
   4 Subject: [PATCH 09/10] net: mtk_eth_soc: move and correct link timer
   5  programming
   6
   7 Program the link timer appropriately for the interface mode being
   8 used, using the newly introduced phylink helper that provides the
   9 nanosecond link timer interval.
  10
  11 The intervals are 1.6ms for SGMII based protocols and 10ms for
  12 802.3z based protocols.
  13
  14 Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
  15 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  16 ---
  17  drivers/net/ethernet/mediatek/mtk_sgmii.c | 13 ++++++++-----
  18  1 file changed, 8 insertions(+), 5 deletions(-)
  19
  20 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
  21 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
  22 @@ -36,10 +36,6 @@ static void mtk_pcs_get_state(struct phy
  23  /* For SGMII interface mode */
  24  static void mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs)
  25  {
  26 -       /* Setup the link timer and QPHY power up inside SGMIISYS */
  27 -       regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
  28 -                    SGMII_LINK_TIMER_DEFAULT);
  29 -
  30         regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
  31                            SGMII_REMOTE_FAULT_DIS, SGMII_REMOTE_FAULT_DIS);
  32
  33 @@ -69,8 +65,8 @@ static int mtk_pcs_config(struct phylink
  34                           bool permit_pause_to_mac)
  35  {
  36         struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
  37 +       int advertise, link_timer;
  38         unsigned int rgc3;
  39 -       int advertise;
  40         bool changed;
  41
  42         if (interface == PHY_INTERFACE_MODE_2500BASEX)
  43 @@ -83,6 +79,10 @@ static int mtk_pcs_config(struct phylink
  44         if (advertise < 0)
  45                 return advertise;
  46
  47 +       link_timer = phylink_get_link_timer_ns(interface);
  48 +       if (link_timer < 0)
  49 +               return link_timer;
  50 +
  51         /* Configure the underlying interface speed */
  52         regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
  53                            RG_PHY_SPEED_3_125G, rgc3);
  54 @@ -91,6 +91,9 @@ static int mtk_pcs_config(struct phylink
  55         regmap_update_bits_check(mpcs->regmap, SGMSYS_PCS_ADVERTISE,
  56                                  SGMII_ADVERTISE, advertise, &changed);
  57
  58 +       /* Setup the link timer and QPHY power up inside SGMIISYS */
  59 +       regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, link_timer / 2 / 8);
  60 +
  61         /* Setup SGMIISYS with the determined property */
  62         if (interface != PHY_INTERFACE_MODE_SGMII)
  63                 mtk_pcs_setup_mode_force(mpcs, interface);