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1 From 875ec5b67ab88e969b171e6e9ea803e3ed759614 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
3 Date: Mon, 22 Apr 2024 10:15:10 +0300
4 Subject: [PATCH 03/15] net: dsa: mt7530: rename p5_intf_sel and use only for
5 MT7530 switch
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 The p5_intf_sel pointer is used to store the information of whether PHY
11 muxing is used or not. PHY muxing is a feature specific to port 5 of the
12 MT7530 switch. Do not use it for other switch models.
13
14 Rename the pointer to p5_mode to store the mode the port is being used in.
15 Rename the p5_interface_select enum to mt7530_p5_mode, the string
16 representation to mt7530_p5_mode_str, and the enum elements.
17
18 If PHY muxing is not detected, the default mode, GMAC5, will be used.
19
20 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
21 ---
22 drivers/net/dsa/mt7530.c | 62 +++++++++++++++++-----------------------
23 drivers/net/dsa/mt7530.h | 15 +++++-----
24 2 files changed, 33 insertions(+), 44 deletions(-)
25
26 --- a/drivers/net/dsa/mt7530.c
27 +++ b/drivers/net/dsa/mt7530.c
28 @@ -857,19 +857,15 @@ mt7530_set_ageing_time(struct dsa_switch
29 return 0;
30 }
31
32 -static const char *p5_intf_modes(unsigned int p5_interface)
33 +static const char *mt7530_p5_mode_str(unsigned int mode)
34 {
35 - switch (p5_interface) {
36 - case P5_DISABLED:
37 - return "DISABLED";
38 - case P5_INTF_SEL_PHY_P0:
39 - return "PHY P0";
40 - case P5_INTF_SEL_PHY_P4:
41 - return "PHY P4";
42 - case P5_INTF_SEL_GMAC5:
43 - return "GMAC5";
44 + switch (mode) {
45 + case MUX_PHY_P0:
46 + return "MUX PHY P0";
47 + case MUX_PHY_P4:
48 + return "MUX PHY P4";
49 default:
50 - return "unknown";
51 + return "GMAC5";
52 }
53 }
54
55 @@ -886,23 +882,23 @@ static void mt7530_setup_port5(struct ds
56 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
57 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
58
59 - switch (priv->p5_intf_sel) {
60 - case P5_INTF_SEL_PHY_P0:
61 - /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
62 + switch (priv->p5_mode) {
63 + /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
64 + case MUX_PHY_P0:
65 val |= MHWTRAP_PHY0_SEL;
66 fallthrough;
67 - case P5_INTF_SEL_PHY_P4:
68 - /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
69 +
70 + /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
71 + case MUX_PHY_P4:
72 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
73
74 /* Setup the MAC by default for the cpu port */
75 mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
76 break;
77 - case P5_INTF_SEL_GMAC5:
78 - /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
79 - val &= ~MHWTRAP_P5_DIS;
80 - break;
81 +
82 + /* GMAC5: P5 -> SoC MAC or external PHY */
83 default:
84 + val &= ~MHWTRAP_P5_DIS;
85 break;
86 }
87
88 @@ -930,8 +926,8 @@ static void mt7530_setup_port5(struct ds
89
90 mt7530_write(priv, MT7530_MHWTRAP, val);
91
92 - dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
93 - val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
94 + dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val,
95 + mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface));
96
97 mutex_unlock(&priv->reg_mutex);
98 }
99 @@ -2476,13 +2472,11 @@ mt7530_setup(struct dsa_switch *ds)
100 if (ret)
101 return ret;
102
103 - /* Setup port 5 */
104 - if (!dsa_is_unused_port(ds, 5)) {
105 - priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
106 - } else {
107 + /* Check for PHY muxing on port 5 */
108 + if (dsa_is_unused_port(ds, 5)) {
109 /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY.
110 - * Set priv->p5_intf_sel to the appropriate value if PHY muxing
111 - * is detected.
112 + * Set priv->p5_mode to the appropriate value if PHY muxing is
113 + * detected.
114 */
115 for_each_child_of_node(dn, mac_np) {
116 if (!of_device_is_compatible(mac_np,
117 @@ -2506,17 +2500,16 @@ mt7530_setup(struct dsa_switch *ds)
118 }
119 id = of_mdio_parse_addr(ds->dev, phy_node);
120 if (id == 0)
121 - priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
122 + priv->p5_mode = MUX_PHY_P0;
123 if (id == 4)
124 - priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
125 + priv->p5_mode = MUX_PHY_P4;
126 }
127 of_node_put(mac_np);
128 of_node_put(phy_node);
129 break;
130 }
131
132 - if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 ||
133 - priv->p5_intf_sel == P5_INTF_SEL_PHY_P4)
134 + if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
135 mt7530_setup_port5(ds, interface);
136 }
137
138 @@ -2654,9 +2647,6 @@ mt7531_setup(struct dsa_switch *ds)
139 MT7531_EXT_P_MDIO_12);
140 }
141
142 - if (!dsa_is_unused_port(ds, 5))
143 - priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
144 -
145 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
146 MT7531_GPIO0_INTERRUPT);
147
148 --- a/drivers/net/dsa/mt7530.h
149 +++ b/drivers/net/dsa/mt7530.h
150 @@ -708,12 +708,11 @@ struct mt7530_port {
151 struct phylink_pcs *sgmii_pcs;
152 };
153
154 -/* Port 5 interface select definitions */
155 -enum p5_interface_select {
156 - P5_DISABLED,
157 - P5_INTF_SEL_PHY_P0,
158 - P5_INTF_SEL_PHY_P4,
159 - P5_INTF_SEL_GMAC5,
160 +/* Port 5 mode definitions of the MT7530 switch */
161 +enum mt7530_p5_mode {
162 + GMAC5,
163 + MUX_PHY_P0,
164 + MUX_PHY_P4,
165 };
166
167 struct mt7530_priv;
168 @@ -776,7 +775,7 @@ struct mt753x_info {
169 * @ports: Holding the state among ports
170 * @reg_mutex: The lock for protecting among process accessing
171 * registers
172 - * @p5_intf_sel: Holding the current port 5 interface select
173 + * @p5_mode: Holding the current mode of port 5 of the MT7530 switch
174 * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
175 * has got SGMII
176 * @irq: IRQ number of the switch
177 @@ -798,7 +797,7 @@ struct mt7530_priv {
178 const struct mt753x_info *info;
179 unsigned int id;
180 bool mcm;
181 - enum p5_interface_select p5_intf_sel;
182 + enum mt7530_p5_mode p5_mode;
183 bool p5_sgmii;
184 u8 mirror_rx;
185 u8 mirror_tx;
Staging tree of Zoltan Herpai