5fbd85c1e7e5cf290619844c43cb408e6ece1696
[openwrt/openwrt.git] /
1 From dcb1e63fbc695c3971d7207238a78f66355a2f9a Mon Sep 17 00:00:00 2001
2 From: Luo Jie <quic_luoj@quicinc.com>
3 Date: Thu, 7 Nov 2024 17:50:26 +0800
4 Subject: [PATCH 5/5] arm64: dts: qcom: Update IPQ9574 xo_board_clk to use
5 fixed factor clock
6
7 xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output clock
8 48 MHZ (also being the reference clock of CMN PLL) divided 2 by analog
9 block routing channel.
10
11 Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
12 ---
13 arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 7 ++++++-
14 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 3 ++-
15 2 files changed, 8 insertions(+), 2 deletions(-)
16
17 diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
18 index 78f6a2e053d5..9a8692377176 100644
19 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
20 +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
21 @@ -174,8 +174,13 @@ &ref_48mhz_clk {
22 clock-mult = <1>;
23 };
24
25 +/*
26 + * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed
27 + * from WiFi output clock 48 MHZ divided by 2.
28 + */
29 &xo_board_clk {
30 - clock-frequency = <24000000>;
31 + clock-div = <2>;
32 + clock-mult = <1>;
33 };
34
35 &xo_clk {
36 diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
37 index dc4965abff58..376b75976524 100644
38 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
39 +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
40 @@ -34,7 +34,8 @@ sleep_clk: sleep-clk {
41 };
42
43 xo_board_clk: xo-board-clk {
44 - compatible = "fixed-clock";
45 + compatible = "fixed-factor-clock";
46 + clocks = <&ref_48mhz_clk>;
47 #clock-cells = <0>;
48 };
49
50 --
51 2.45.2
52