git.openwrt.org Git - openwrt/staging/dangole.git/blob

   1 From 9994241ac97cb84d1df98fdc172d3cc6b04b11bf Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
   3 Date: Fri, 9 Nov 2018 09:56:49 +0100
   4 Subject: [PATCH] ARM: dts: BCM5301X: Describe Northstar pins mux controller
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This describes hardware & will allow referencing pin functions. The
  10 first usage is UART1 which allows supporting devices using it.
  11
  12 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  13 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  14 ---
  15  arch/arm/boot/dts/bcm5301x.dtsi | 44 +++++++++++++++++++++++++++++++++++++++++
  16  1 file changed, 44 insertions(+)
  17
  18 --- a/arch/arm/boot/dts/bcm5301x.dtsi
  19 +++ b/arch/arm/boot/dts/bcm5301x.dtsi
  20 @@ -37,6 +37,8 @@
  21                         reg = <0x0400 0x100>;
  22                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  23                         clocks = <&iprocslow>;
  24 +                       pinctrl-names = "default";
  25 +                       pinctrl-0 = <&pinmux_uart1>;
  26                         status = "disabled";
  27                 };
  28         };
  29 @@ -391,6 +393,48 @@
  30                 status = "disabled";
  31         };
  32
  33 +       dmu@1800c000 {
  34 +               compatible = "simple-bus";
  35 +               ranges = <0 0x1800c000 0x1000>;
  36 +               #address-cells = <1>;
  37 +               #size-cells = <1>;
  38 +
  39 +               cru@100 {
  40 +                       compatible = "simple-bus";
  41 +                       reg = <0x100 0x1a4>;
  42 +                       ranges;
  43 +                       #address-cells = <1>;
  44 +                       #size-cells = <1>;
  45 +
  46 +                       pin-controller@1c0 {
  47 +                               compatible = "brcm,bcm4708-pinmux";
  48 +                               reg = <0x1c0 0x24>;
  49 +                               reg-names = "cru_gpio_control";
  50 +
  51 +                               spi-pins {
  52 +                                       groups = "spi_grp";
  53 +                                       function = "spi";
  54 +                               };
  55 +
  56 +                               i2c {
  57 +                                       groups = "i2c_grp";
  58 +                                       function = "i2c";
  59 +                               };
  60 +
  61 +                               pwm {
  62 +                                       groups = "pwm0_grp", "pwm1_grp",
  63 +                                                "pwm2_grp", "pwm3_grp";
  64 +                                       function = "pwm";
  65 +                               };
  66 +
  67 +                               pinmux_uart1: uart1 {
  68 +                                       groups = "uart1_grp";
  69 +                                       function = "uart1";
  70 +                               };
  71 +                       };
  72 +               };
  73 +       };
  74 +
  75         lcpll0: lcpll0@1800c100 {
  76                 #clock-cells = <1>;
  77                 compatible = "brcm,nsp-lcpll0";