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1 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
2 Date: Fri, 5 Feb 2021 21:59:51 +0100
3 Subject: [PATCH 2/2] net: broadcom: bcm4908enet: add BCM4908 controller driver
4
5 BCM4908 SoCs family uses Ethernel controller that includes UniMAC but
6 uses different DMA engine (than other controllers) and requires
7 different programming.
8
9 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
10 ---
11 MAINTAINERS | 9 +
12 drivers/net/ethernet/broadcom/Kconfig | 8 +
13 drivers/net/ethernet/broadcom/Makefile | 1 +
14 drivers/net/ethernet/broadcom/bcm4908enet.c | 676 ++++++++++++++++++++
15 drivers/net/ethernet/broadcom/bcm4908enet.h | 96 +++
16 5 files changed, 790 insertions(+)
17 create mode 100644 drivers/net/ethernet/broadcom/bcm4908enet.c
18 create mode 100644 drivers/net/ethernet/broadcom/bcm4908enet.h
19
20 --- a/MAINTAINERS
21 +++ b/MAINTAINERS
22 @@ -3207,6 +3207,15 @@ F: Documentation/devicetree/bindings/mip
23 F: arch/mips/bcm47xx/*
24 F: arch/mips/include/asm/mach-bcm47xx/*
25
26 +BROADCOM BCM4908 ETHERNET DRIVER
27 +M: Rafał Miłecki <rafal@milecki.pl>
28 +M: bcm-kernel-feedback-list@broadcom.com
29 +L: netdev@vger.kernel.org
30 +S: Maintained
31 +F: Documentation/devicetree/bindings/net/brcm,bcm4908enet.yaml
32 +F: drivers/net/ethernet/broadcom/bcm4908enet.*
33 +F: drivers/net/ethernet/broadcom/unimac.h
34 +
35 BROADCOM BCM5301X ARM ARCHITECTURE
36 M: Hauke Mehrtens <hauke@hauke-m.de>
37 M: Rafał Miłecki <zajec5@gmail.com>
38 --- a/drivers/net/ethernet/broadcom/Kconfig
39 +++ b/drivers/net/ethernet/broadcom/Kconfig
40 @@ -51,6 +51,14 @@ config B44_PCI
41 depends on B44_PCI_AUTOSELECT && B44_PCICORE_AUTOSELECT
42 default y
43
44 +config BCM4908ENET
45 + tristate "Broadcom BCM4908 internal mac support"
46 + depends on ARCH_BCM4908 || COMPILE_TEST
47 + default y
48 + help
49 + This driver supports Ethernet controller integrated into Broadcom
50 + BCM4908 family SoCs.
51 +
52 config BCM63XX_ENET
53 tristate "Broadcom 63xx internal mac support"
54 depends on BCM63XX
55 --- a/drivers/net/ethernet/broadcom/Makefile
56 +++ b/drivers/net/ethernet/broadcom/Makefile
57 @@ -4,6 +4,7 @@
58 #
59
60 obj-$(CONFIG_B44) += b44.o
61 +obj-$(CONFIG_BCM4908ENET) += bcm4908enet.o
62 obj-$(CONFIG_BCM63XX_ENET) += bcm63xx_enet.o
63 obj-$(CONFIG_BCMGENET) += genet/
64 obj-$(CONFIG_BNX2) += bnx2.o
65 --- /dev/null
66 +++ b/drivers/net/ethernet/broadcom/bcm4908enet.c
67 @@ -0,0 +1,676 @@
68 +// SPDX-License-Identifier: GPL-2.0-only
69 +/*
70 + * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl>
71 + */
72 +
73 +#include <linux/delay.h>
74 +#include <linux/etherdevice.h>
75 +#include <linux/interrupt.h>
76 +#include <linux/module.h>
77 +#include <linux/of.h>
78 +#include <linux/platform_device.h>
79 +#include <linux/slab.h>
80 +#include <linux/string.h>
81 +
82 +#include "bcm4908enet.h"
83 +#include "unimac.h"
84 +
85 +#define ENET_DMA_CH_RX_CFG ENET_DMA_CH0_CFG
86 +#define ENET_DMA_CH_TX_CFG ENET_DMA_CH1_CFG
87 +#define ENET_DMA_CH_RX_STATE_RAM ENET_DMA_CH0_STATE_RAM
88 +#define ENET_DMA_CH_TX_STATE_RAM ENET_DMA_CH1_STATE_RAM
89 +
90 +#define ENET_TX_BDS_NUM 200
91 +#define ENET_RX_BDS_NUM 200
92 +#define ENET_RX_BDS_NUM_MAX 8192
93 +
94 +#define ENET_DMA_INT_DEFAULTS (ENET_DMA_CH_CFG_INT_DONE | \
95 + ENET_DMA_CH_CFG_INT_NO_DESC | \
96 + ENET_DMA_CH_CFG_INT_BUFF_DONE)
97 +#define ENET_DMA_MAX_BURST_LEN 8 /* in 64 bit words */
98 +
99 +#define ENET_MTU_MIN 60
100 +#define ENET_MTU_MAX 1500 /* Is it possible to support 2044? */
101 +#define ENET_MTU_MAX_EXTRA_SIZE 32 /* L2 */
102 +
103 +struct bcm4908enet_dma_ring_bd {
104 + __le32 ctl;
105 + __le32 addr;
106 +} __packed;
107 +
108 +struct bcm4908enet_dma_ring_slot {
109 + struct sk_buff *skb;
110 + unsigned int len;
111 + dma_addr_t dma_addr;
112 +};
113 +
114 +struct bcm4908enet_dma_ring {
115 + int is_tx;
116 + int read_idx;
117 + int write_idx;
118 + int length;
119 + u16 cfg_block;
120 + u16 st_ram_block;
121 +
122 + union {
123 + void *cpu_addr;
124 + struct bcm4908enet_dma_ring_bd *buf_desc;
125 + };
126 + dma_addr_t dma_addr;
127 +
128 + struct bcm4908enet_dma_ring_slot *slots;
129 +};
130 +
131 +struct bcm4908enet {
132 + struct device *dev;
133 + struct net_device *netdev;
134 + struct napi_struct napi;
135 + void __iomem *base;
136 +
137 + struct bcm4908enet_dma_ring tx_ring;
138 + struct bcm4908enet_dma_ring rx_ring;
139 +};
140 +
141 +/***
142 + * R/W ops
143 + */
144 +
145 +static inline u32 enet_read(struct bcm4908enet *enet, u16 offset)
146 +{
147 + return readl(enet->base + offset);
148 +}
149 +
150 +static inline void enet_write(struct bcm4908enet *enet, u16 offset, u32 value)
151 +{
152 + writel(value, enet->base + offset);
153 +}
154 +
155 +static inline void enet_maskset(struct bcm4908enet *enet, u16 offset, u32 mask, u32 set)
156 +{
157 + u32 val;
158 +
159 + WARN_ON(set & ~mask);
160 +
161 + val = enet_read(enet, offset);
162 + val = (val & ~mask) | (set & mask);
163 + enet_write(enet, offset, val);
164 +}
165 +
166 +static inline void enet_set(struct bcm4908enet *enet, u16 offset, u32 set)
167 +{
168 + enet_maskset(enet, offset, set, set);
169 +}
170 +
171 +static inline u32 enet_umac_read(struct bcm4908enet *enet, u16 offset)
172 +{
173 + return enet_read(enet, ENET_UNIMAC + offset);
174 +}
175 +
176 +static inline void enet_umac_write(struct bcm4908enet *enet, u16 offset, u32 value)
177 +{
178 + enet_write(enet, ENET_UNIMAC + offset, value);
179 +}
180 +
181 +static inline void enet_umac_maskset(struct bcm4908enet *enet, u16 offset, u32 mask, u32 set)
182 +{
183 + enet_maskset(enet, ENET_UNIMAC + offset, mask, set);
184 +}
185 +
186 +static inline void enet_umac_set(struct bcm4908enet *enet, u16 offset, u32 set)
187 +{
188 + enet_set(enet, ENET_UNIMAC + offset, set);
189 +}
190 +
191 +/***
192 + * Helpers
193 + */
194 +
195 +static void bcm4908enet_intrs_on(struct bcm4908enet *enet)
196 +{
197 + enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS);
198 +}
199 +
200 +static void bcm4908enet_intrs_off(struct bcm4908enet *enet)
201 +{
202 + enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, 0);
203 +}
204 +
205 +static void bcm4908enet_intrs_ack(struct bcm4908enet *enet)
206 +{
207 + enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);
208 +}
209 +
210 +/***
211 + * DMA
212 + */
213 +
214 +static int bcm4908_dma_alloc_buf_descs(struct bcm4908enet *enet, struct bcm4908enet_dma_ring *ring)
215 +{
216 + int size = ring->length * sizeof(struct bcm4908enet_dma_ring_bd);
217 + struct device *dev = enet->dev;
218 +
219 + ring->cpu_addr = dma_alloc_coherent(dev, size, &ring->dma_addr, GFP_KERNEL);
220 + if (!ring->cpu_addr)
221 + return -ENOMEM;
222 +
223 + if (((uintptr_t)ring->cpu_addr) & (0x40 - 1)) {
224 + dev_err(dev, "Invalid DMA ring alignment\n");
225 + goto err_free_buf_descs;
226 + }
227 +
228 + ring->slots = kzalloc(ring->length * sizeof(*ring->slots), GFP_KERNEL);
229 + if (!ring->slots)
230 + goto err_free_buf_descs;
231 +
232 + memset(ring->cpu_addr, 0, size);
233 +
234 + ring->read_idx = 0;
235 + ring->write_idx = 0;
236 +
237 + return 0;
238 +
239 +err_free_buf_descs:
240 + dma_free_coherent(dev, size, ring->cpu_addr, ring->dma_addr);
241 + return -ENOMEM;
242 +}
243 +
244 +static void bcm4908enet_dma_free(struct bcm4908enet *enet)
245 +{
246 + struct bcm4908enet_dma_ring *tx_ring = &enet->tx_ring;
247 + struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;
248 + struct device *dev = enet->dev;
249 + int size;
250 +
251 + size = rx_ring->length * sizeof(struct bcm4908enet_dma_ring_bd);
252 + if (rx_ring->cpu_addr)
253 + dma_free_coherent(dev, size, rx_ring->cpu_addr, rx_ring->dma_addr);
254 + kfree(rx_ring->slots);
255 +
256 + size = tx_ring->length * sizeof(struct bcm4908enet_dma_ring_bd);
257 + if (tx_ring->cpu_addr)
258 + dma_free_coherent(dev, size, tx_ring->cpu_addr, tx_ring->dma_addr);
259 + kfree(tx_ring->slots);
260 +}
261 +
262 +static int bcm4908enet_dma_alloc(struct bcm4908enet *enet)
263 +{
264 + struct bcm4908enet_dma_ring *tx_ring = &enet->tx_ring;
265 + struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;
266 + struct device *dev = enet->dev;
267 + int err;
268 +
269 + tx_ring->length = ENET_TX_BDS_NUM;
270 + tx_ring->is_tx = 1;
271 + tx_ring->cfg_block = ENET_DMA_CH_TX_CFG;
272 + tx_ring->st_ram_block = ENET_DMA_CH_TX_STATE_RAM;
273 + err = bcm4908_dma_alloc_buf_descs(enet, tx_ring);
274 + if (err) {
275 + dev_err(dev, "Failed to alloc TX buf descriptors: %d\n", err);
276 + return err;
277 + }
278 +
279 + rx_ring->length = ENET_RX_BDS_NUM;
280 + rx_ring->is_tx = 0;
281 + rx_ring->cfg_block = ENET_DMA_CH_RX_CFG;
282 + rx_ring->st_ram_block = ENET_DMA_CH_RX_STATE_RAM;
283 + err = bcm4908_dma_alloc_buf_descs(enet, rx_ring);
284 + if (err) {
285 + dev_err(dev, "Failed to alloc RX buf descriptors: %d\n", err);
286 + bcm4908enet_dma_free(enet);
287 + return err;
288 + }
289 +
290 + return 0;
291 +}
292 +
293 +static void bcm4908enet_dma_reset(struct bcm4908enet *enet)
294 +{
295 + struct bcm4908enet_dma_ring *rings[] = { &enet->rx_ring, &enet->tx_ring };
296 + int i;
297 +
298 + /* Disable the DMA controller and channel */
299 + for (i = 0; i < ARRAY_SIZE(rings); i++)
300 + enet_write(enet, rings[i]->cfg_block + ENET_DMA_CH_CFG, 0);
301 + enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN, 0);
302 +
303 + /* Reset channels state */
304 + for (i = 0; i < ARRAY_SIZE(rings); i++) {
305 + struct bcm4908enet_dma_ring *ring = rings[i];
306 +
307 + enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0);
308 + enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0);
309 + enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0);
310 + enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0);
311 + }
312 +}
313 +
314 +static int bcm4908enet_dma_alloc_rx_buf(struct bcm4908enet *enet, unsigned int idx)
315 +{
316 + struct bcm4908enet_dma_ring_bd *buf_desc = &enet->rx_ring.buf_desc[idx];
317 + struct bcm4908enet_dma_ring_slot *slot = &enet->rx_ring.slots[idx];
318 + struct device *dev = enet->dev;
319 + u32 tmp;
320 + int err;
321 +
322 + slot->len = ENET_MTU_MAX + ENET_MTU_MAX_EXTRA_SIZE;
323 +
324 + slot->skb = netdev_alloc_skb(enet->netdev, slot->len);
325 + if (!slot->skb)
326 + return -ENOMEM;
327 +
328 + slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE);
329 + err = dma_mapping_error(dev, slot->dma_addr);
330 + if (err) {
331 + dev_err(dev, "Failed to map DMA buffer: %d\n", err);
332 + kfree_skb(slot->skb);
333 + slot->skb = NULL;
334 + return err;
335 + }
336 +
337 + tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
338 + tmp |= DMA_CTL_STATUS_OWN;
339 + if (idx == enet->rx_ring.length - 1)
340 + tmp |= DMA_CTL_STATUS_WRAP;
341 + buf_desc->ctl = cpu_to_le32(tmp);
342 + buf_desc->addr = cpu_to_le32(slot->dma_addr);
343 +
344 + return 0;
345 +}
346 +
347 +static void bcm4908enet_dma_ring_init(struct bcm4908enet *enet,
348 + struct bcm4908enet_dma_ring *ring)
349 +{
350 + int reset_channel = 0; /* We support only 1 main channel (with TX and RX) */
351 + int reset_subch = ring->is_tx ? 1 : 0;
352 +
353 + /* Reset the DMA channel */
354 + enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, BIT(reset_channel * 2 + reset_subch));
355 + enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, 0);
356 +
357 + enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);
358 + enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN);
359 + enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);
360 +
361 + enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR,
362 + (uint32_t)ring->dma_addr);
363 +}
364 +
365 +static void bcm4908enet_dma_uninit(struct bcm4908enet *enet)
366 +{
367 + struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;
368 + struct bcm4908enet_dma_ring_slot *slot;
369 + struct device *dev = enet->dev;
370 + int i;
371 +
372 + for (i = rx_ring->length - 1; i >= 0; i--) {
373 + slot = &rx_ring->slots[i];
374 + if (!slot->skb)
375 + continue;
376 + dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE);
377 + kfree_skb(slot->skb);
378 + slot->skb = NULL;
379 + }
380 +}
381 +
382 +static int bcm4908enet_dma_init(struct bcm4908enet *enet)
383 +{
384 + struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;
385 + struct device *dev = enet->dev;
386 + int err;
387 + int i;
388 +
389 + for (i = 0; i < rx_ring->length; i++) {
390 + err = bcm4908enet_dma_alloc_rx_buf(enet, i);
391 + if (err) {
392 + dev_err(dev, "Failed to alloc RX buffer: %d\n", err);
393 + bcm4908enet_dma_uninit(enet);
394 + return err;
395 + }
396 + }
397 +
398 + bcm4908enet_dma_ring_init(enet, &enet->tx_ring);
399 + bcm4908enet_dma_ring_init(enet, &enet->rx_ring);
400 +
401 + return 0;
402 +}
403 +
404 +static void bcm4908enet_dma_tx_ring_ensable(struct bcm4908enet *enet,
405 + struct bcm4908enet_dma_ring *ring)
406 +{
407 + enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);
408 +}
409 +
410 +static void bcm4908enet_dma_tx_ring_disable(struct bcm4908enet *enet,
411 + struct bcm4908enet_dma_ring *ring)
412 +{
413 + enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);
414 +}
415 +
416 +static void bcm4908enet_dma_rx_ring_enable(struct bcm4908enet *enet,
417 + struct bcm4908enet_dma_ring *ring)
418 +{
419 + enet_set(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);
420 +}
421 +
422 +static void bcm4908enet_dma_rx_ring_disable(struct bcm4908enet *enet,
423 + struct bcm4908enet_dma_ring *ring)
424 +{
425 + unsigned long deadline;
426 + u32 tmp;
427 +
428 + enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);
429 +
430 + deadline = jiffies + usecs_to_jiffies(2000);
431 + do {
432 + tmp = enet_read(enet, ring->cfg_block + ENET_DMA_CH_CFG);
433 + if (!(tmp & ENET_DMA_CH_CFG_ENABLE))
434 + return;
435 + enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);
436 + usleep_range(10, 30);
437 + } while (!time_after_eq(jiffies, deadline));
438 +
439 + dev_warn(enet->dev, "Timeout waiting for DMA TX stop\n");
440 +}
441 +
442 +/***
443 + * Ethernet driver
444 + */
445 +
446 +static void bcm4908enet_gmac_init(struct bcm4908enet *enet)
447 +{
448 + u32 cmd;
449 +
450 + cmd = enet_umac_read(enet, UMAC_CMD);
451 + enet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET);
452 + enet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET);
453 +
454 + enet_set(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH);
455 + enet_maskset(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH, 0);
456 +
457 + enet_set(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB);
458 + enet_maskset(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB, 0);
459 +
460 + cmd = enet_umac_read(enet, UMAC_CMD);
461 + cmd &= ~(CMD_SPEED_MASK << CMD_SPEED_SHIFT);
462 + cmd &= ~CMD_TX_EN;
463 + cmd &= ~CMD_RX_EN;
464 + cmd |= CMD_SPEED_1000 << CMD_SPEED_SHIFT;
465 + enet_umac_write(enet, UMAC_CMD, cmd);
466 +
467 + enet_maskset(enet, ENET_GMAC_STATUS,
468 + ENET_GMAC_STATUS_ETH_SPEED_MASK |
469 + ENET_GMAC_STATUS_HD |
470 + ENET_GMAC_STATUS_AUTO_CFG_EN |
471 + ENET_GMAC_STATUS_LINK_UP,
472 + ENET_GMAC_STATUS_ETH_SPEED_1000 |
473 + ENET_GMAC_STATUS_AUTO_CFG_EN |
474 + ENET_GMAC_STATUS_LINK_UP);
475 +}
476 +
477 +static irqreturn_t bcm4908enet_irq_handler(int irq, void *dev_id)
478 +{
479 + struct bcm4908enet *enet = dev_id;
480 +
481 + bcm4908enet_intrs_off(enet);
482 + bcm4908enet_intrs_ack(enet);
483 +
484 + napi_schedule(&enet->napi);
485 +
486 + return IRQ_HANDLED;
487 +}
488 +
489 +static int bcm4908enet_open(struct net_device *netdev)
490 +{
491 + struct bcm4908enet *enet = netdev_priv(netdev);
492 + struct device *dev = enet->dev;
493 + int err;
494 +
495 + err = request_irq(netdev->irq, bcm4908enet_irq_handler, 0, "enet", enet);
496 + if (err) {
497 + dev_err(dev, "Failed to request IRQ %d: %d\n", netdev->irq, err);
498 + return err;
499 + }
500 +
501 + bcm4908enet_gmac_init(enet);
502 + bcm4908enet_dma_reset(enet);
503 + bcm4908enet_dma_init(enet);
504 +
505 + enet_umac_set(enet, UMAC_CMD, CMD_TX_EN | CMD_RX_EN);
506 +
507 + enet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN);
508 + enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0);
509 + bcm4908enet_dma_rx_ring_enable(enet, &enet->rx_ring);
510 +
511 + napi_enable(&enet->napi);
512 + netif_carrier_on(netdev);
513 + netif_start_queue(netdev);
514 +
515 + bcm4908enet_intrs_ack(enet);
516 + bcm4908enet_intrs_on(enet);
517 +
518 + return 0;
519 +}
520 +
521 +static int bcm4908enet_stop(struct net_device *netdev)
522 +{
523 + struct bcm4908enet *enet = netdev_priv(netdev);
524 +
525 + netif_stop_queue(netdev);
526 + netif_carrier_off(netdev);
527 + napi_disable(&enet->napi);
528 +
529 + bcm4908enet_dma_rx_ring_disable(enet, &enet->rx_ring);
530 + bcm4908enet_dma_tx_ring_disable(enet, &enet->tx_ring);
531 +
532 + bcm4908enet_dma_uninit(enet);
533 +
534 + free_irq(enet->netdev->irq, enet);
535 +
536 + return 0;
537 +}
538 +
539 +static int bcm4908enet_start_xmit(struct sk_buff *skb, struct net_device *netdev)
540 +{
541 + struct bcm4908enet *enet = netdev_priv(netdev);
542 + struct bcm4908enet_dma_ring *ring = &enet->tx_ring;
543 + struct bcm4908enet_dma_ring_slot *slot;
544 + struct device *dev = enet->dev;
545 + struct bcm4908enet_dma_ring_bd *buf_desc;
546 + int free_buf_descs;
547 + u32 tmp;
548 +
549 + /* Free transmitted skbs */
550 + while (ring->read_idx != ring->write_idx) {
551 + buf_desc = &ring->buf_desc[ring->read_idx];
552 + if (buf_desc->ctl & DMA_CTL_STATUS_OWN)
553 + break;
554 + slot = &ring->slots[ring->read_idx];
555 +
556 + dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE);
557 + dev_kfree_skb(slot->skb);
558 + if (++ring->read_idx == ring->length)
559 + ring->read_idx = 0;
560 + }
561 +
562 + /* Don't use the last empty buf descriptor */
563 + if (ring->read_idx <= ring->write_idx)
564 + free_buf_descs = ring->read_idx - ring->write_idx + ring->length;
565 + else
566 + free_buf_descs = ring->read_idx - ring->write_idx;
567 + if (free_buf_descs < 2)
568 + return NETDEV_TX_BUSY;
569 +
570 + /* Hardware removes OWN bit after sending data */
571 + buf_desc = &ring->buf_desc[ring->write_idx];
572 + if (unlikely(le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)) {
573 + netif_stop_queue(netdev);
574 + return NETDEV_TX_BUSY;
575 + }
576 +
577 + slot = &ring->slots[ring->write_idx];
578 + slot->skb = skb;
579 + slot->len = skb->len;
580 + slot->dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE);
581 + if (unlikely(dma_mapping_error(dev, slot->dma_addr)))
582 + return NETDEV_TX_BUSY;
583 +
584 + tmp = skb->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
585 + tmp |= DMA_CTL_STATUS_OWN;
586 + tmp |= DMA_CTL_STATUS_SOP;
587 + tmp |= DMA_CTL_STATUS_EOP;
588 + tmp |= DMA_CTL_STATUS_APPEND_CRC;
589 + if (ring->write_idx + 1 == ring->length - 1)
590 + tmp |= DMA_CTL_STATUS_WRAP;
591 +
592 + buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr);
593 + buf_desc->ctl = cpu_to_le32(tmp);
594 +
595 + bcm4908enet_dma_tx_ring_ensable(enet, &enet->tx_ring);
596 +
597 + if (++ring->write_idx == ring->length - 1)
598 + ring->write_idx = 0;
599 + enet->netdev->stats.tx_bytes += skb->len;
600 + enet->netdev->stats.tx_packets++;
601 +
602 + return NETDEV_TX_OK;
603 +}
604 +
605 +static int bcm4908enet_poll(struct napi_struct *napi, int weight)
606 +{
607 + struct bcm4908enet *enet = container_of(napi, struct bcm4908enet, napi);
608 + struct device *dev = enet->dev;
609 + int handled = 0;
610 +
611 + while (handled < weight) {
612 + struct bcm4908enet_dma_ring_bd *buf_desc;
613 + struct bcm4908enet_dma_ring_slot slot;
614 + u32 ctl;
615 + int len;
616 + int err;
617 +
618 + buf_desc = &enet->rx_ring.buf_desc[enet->rx_ring.read_idx];
619 + ctl = le32_to_cpu(buf_desc->ctl);
620 + if (ctl & DMA_CTL_STATUS_OWN)
621 + break;
622 +
623 + slot = enet->rx_ring.slots[enet->rx_ring.read_idx];
624 +
625 + /* Provide new buffer before unpinning the old one */
626 + err = bcm4908enet_dma_alloc_rx_buf(enet, enet->rx_ring.read_idx);
627 + if (err)
628 + break;
629 +
630 + if (++enet->rx_ring.read_idx == enet->rx_ring.length)
631 + enet->rx_ring.read_idx = 0;
632 +
633 + len = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
634 +
635 + if (len < ENET_MTU_MIN ||
636 + (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {
637 + enet->netdev->stats.rx_dropped++;
638 + break;
639 + }
640 +
641 + dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE);
642 +
643 + skb_put(slot.skb, len - 4 + 2);
644 + slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev);
645 + netif_receive_skb(slot.skb);
646 +
647 + enet->netdev->stats.rx_packets++;
648 + enet->netdev->stats.rx_bytes += len;
649 + }
650 +
651 + if (handled < weight) {
652 + napi_complete_done(napi, handled);
653 + bcm4908enet_intrs_on(enet);
654 + }
655 +
656 + return handled;
657 +}
658 +
659 +static const struct net_device_ops bcm96xx_netdev_ops = {
660 + .ndo_open = bcm4908enet_open,
661 + .ndo_stop = bcm4908enet_stop,
662 + .ndo_start_xmit = bcm4908enet_start_xmit,
663 + .ndo_set_mac_address = eth_mac_addr,
664 +};
665 +
666 +static int bcm4908enet_probe(struct platform_device *pdev)
667 +{
668 + struct device *dev = &pdev->dev;
669 + struct net_device *netdev;
670 + struct bcm4908enet *enet;
671 + int err;
672 +
673 + netdev = devm_alloc_etherdev(dev, sizeof(*enet));
674 + if (!netdev)
675 + return -ENOMEM;
676 +
677 + enet = netdev_priv(netdev);
678 + enet->dev = dev;
679 + enet->netdev = netdev;
680 +
681 + enet->base = devm_platform_ioremap_resource(pdev, 0);
682 + if (IS_ERR(enet->base)) {
683 + dev_err(dev, "Failed to map registers: %ld\n", PTR_ERR(enet->base));
684 + return PTR_ERR(enet->base);
685 + }
686 +
687 + netdev->irq = platform_get_irq_byname(pdev, "rx");
688 + if (netdev->irq < 0)
689 + return netdev->irq;
690 +
691 + dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
692 +
693 + err = bcm4908enet_dma_alloc(enet);
694 + if (err)
695 + return err;
696 +
697 + SET_NETDEV_DEV(netdev, &pdev->dev);
698 + eth_hw_addr_random(netdev);
699 + netdev->netdev_ops = &bcm96xx_netdev_ops;
700 + netdev->min_mtu = ETH_ZLEN;
701 + netdev->mtu = ENET_MTU_MAX;
702 + netdev->max_mtu = ENET_MTU_MAX;
703 + netif_napi_add(netdev, &enet->napi, bcm4908enet_poll, 64);
704 +
705 + err = register_netdev(netdev);
706 + if (err) {
707 + bcm4908enet_dma_free(enet);
708 + return err;
709 + }
710 +
711 + platform_set_drvdata(pdev, enet);
712 +
713 + return 0;
714 +}
715 +
716 +static int bcm4908enet_remove(struct platform_device *pdev)
717 +{
718 + struct bcm4908enet *enet = platform_get_drvdata(pdev);
719 +
720 + unregister_netdev(enet->netdev);
721 + netif_napi_del(&enet->napi);
722 + bcm4908enet_dma_free(enet);
723 +
724 + return 0;
725 +}
726 +
727 +static const struct of_device_id bcm4908enet_of_match[] = {
728 + { .compatible = "brcm,bcm4908enet"},
729 + {},
730 +};
731 +
732 +static struct platform_driver bcm4908enet_driver = {
733 + .driver = {
734 + .name = "bcm4908enet",
735 + .of_match_table = bcm4908enet_of_match,
736 + },
737 + .probe = bcm4908enet_probe,
738 + .remove = bcm4908enet_remove,
739 +};
740 +module_platform_driver(bcm4908enet_driver);
741 +
742 +MODULE_LICENSE("GPL v2");
743 +MODULE_DEVICE_TABLE(of, bcm4908enet_of_match);
744 --- /dev/null
745 +++ b/drivers/net/ethernet/broadcom/bcm4908enet.h
746 @@ -0,0 +1,96 @@
747 +/* SPDX-License-Identifier: GPL-2.0-only */
748 +#ifndef __BCM4908ENET_H
749 +#define __BCM4908ENET_H
750 +
751 +#define ENET_CONTROL 0x000
752 +#define ENET_MIB_CTRL 0x004
753 +#define ENET_MIB_CTRL_CLR_MIB 0x00000001
754 +#define ENET_RX_ERR_MASK 0x008
755 +#define ENET_MIB_MAX_PKT_SIZE 0x00C
756 +#define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff
757 +#define ENET_DIAG_OUT 0x01c
758 +#define ENET_ENABLE_DROP_PKT 0x020
759 +#define ENET_IRQ_ENABLE 0x024
760 +#define ENET_IRQ_ENABLE_OVFL 0x00000001
761 +#define ENET_GMAC_STATUS 0x028
762 +#define ENET_GMAC_STATUS_ETH_SPEED_MASK 0x00000003
763 +#define ENET_GMAC_STATUS_ETH_SPEED_10 0x00000000
764 +#define ENET_GMAC_STATUS_ETH_SPEED_100 0x00000001
765 +#define ENET_GMAC_STATUS_ETH_SPEED_1000 0x00000002
766 +#define ENET_GMAC_STATUS_HD 0x00000004
767 +#define ENET_GMAC_STATUS_AUTO_CFG_EN 0x00000008
768 +#define ENET_GMAC_STATUS_LINK_UP 0x00000010
769 +#define ENET_IRQ_STATUS 0x02c
770 +#define ENET_IRQ_STATUS_OVFL 0x00000001
771 +#define ENET_OVERFLOW_COUNTER 0x030
772 +#define ENET_FLUSH 0x034
773 +#define ENET_FLUSH_RXFIFO_FLUSH 0x00000001
774 +#define ENET_FLUSH_TXFIFO_FLUSH 0x00000002
775 +#define ENET_RSV_SELECT 0x038
776 +#define ENET_BP_FORCE 0x03c
777 +#define ENET_BP_FORCE_FORCE 0x00000001
778 +#define ENET_DMA_RX_OK_TO_SEND_COUNT 0x040
779 +#define ENET_DMA_RX_OK_TO_SEND_COUNT_VAL 0x0000000f
780 +#define ENET_TX_CRC_CTRL 0x044
781 +#define ENET_MIB 0x200
782 +#define ENET_UNIMAC 0x400
783 +#define ENET_DMA 0x800
784 +#define ENET_DMA_CONTROLLER_CFG 0x800
785 +#define ENET_DMA_CTRL_CFG_MASTER_EN 0x00000001
786 +#define ENET_DMA_CTRL_CFG_FLOWC_CH1_EN 0x00000002
787 +#define ENET_DMA_CTRL_CFG_FLOWC_CH3_EN 0x00000004
788 +#define ENET_DMA_FLOWCTL_CH1_THRESH_LO 0x804
789 +#define ENET_DMA_FLOWCTL_CH1_THRESH_HI 0x808
790 +#define ENET_DMA_FLOWCTL_CH1_ALLOC 0x80c
791 +#define ENET_DMA_FLOWCTL_CH1_ALLOC_FORCE 0x80000000
792 +#define ENET_DMA_FLOWCTL_CH3_THRESH_LO 0x810
793 +#define ENET_DMA_FLOWCTL_CH3_THRESH_HI 0x814
794 +#define ENET_DMA_FLOWCTL_CH3_ALLOC 0x818
795 +#define ENET_DMA_FLOWCTL_CH5_THRESH_LO 0x81C
796 +#define ENET_DMA_FLOWCTL_CH5_THRESH_HI 0x820
797 +#define ENET_DMA_FLOWCTL_CH5_ALLOC 0x824
798 +#define ENET_DMA_FLOWCTL_CH7_THRESH_LO 0x828
799 +#define ENET_DMA_FLOWCTL_CH7_THRESH_HI 0x82C
800 +#define ENET_DMA_FLOWCTL_CH7_ALLOC 0x830
801 +#define ENET_DMA_CTRL_CHANNEL_RESET 0x834
802 +#define ENET_DMA_CTRL_CHANNEL_DEBUG 0x838
803 +#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_STATUS 0x840
804 +#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_MASK 0x844
805 +#define ENET_DMA_CH0_CFG 0xa00 /* RX */
806 +#define ENET_DMA_CH1_CFG 0xa10 /* TX */
807 +#define ENET_DMA_CH0_STATE_RAM 0xc00 /* RX */
808 +#define ENET_DMA_CH1_STATE_RAM 0xc10 /* TX */
809 +
810 +#define ENET_DMA_CH_CFG 0x00 /* assorted configuration */
811 +#define ENET_DMA_CH_CFG_ENABLE 0x00000001 /* set to enable channel */
812 +#define ENET_DMA_CH_CFG_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */
813 +#define ENET_DMA_CH_CFG_BURST_HALT 0x00000004 /* idle after finish current memory burst */
814 +#define ENET_DMA_CH_CFG_INT_STAT 0x04 /* interrupts control and status */
815 +#define ENET_DMA_CH_CFG_INT_MASK 0x08 /* interrupts mask */
816 +#define ENET_DMA_CH_CFG_INT_BUFF_DONE 0x00000001 /* buffer done */
817 +#define ENET_DMA_CH_CFG_INT_DONE 0x00000002 /* packet xfer complete */
818 +#define ENET_DMA_CH_CFG_INT_NO_DESC 0x00000004 /* no valid descriptors */
819 +#define ENET_DMA_CH_CFG_INT_RX_ERROR 0x00000008 /* rxdma detect client protocol error */
820 +#define ENET_DMA_CH_CFG_MAX_BURST 0x0c /* max burst length permitted */
821 +#define ENET_DMA_CH_CFG_MAX_BURST_DESCSIZE_SEL 0x00040000 /* DMA Descriptor Size Selection */
822 +#define ENET_DMA_CH_CFG_SIZE 0x10
823 +
824 +#define ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR 0x00 /* descriptor ring start address */
825 +#define ENET_DMA_CH_STATE_RAM_STATE_DATA 0x04 /* state/bytes done/ring offset */
826 +#define ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS 0x08 /* buffer descriptor status and len */
827 +#define ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR 0x0c /* buffer descrpitor current processing */
828 +#define ENET_DMA_CH_STATE_RAM_SIZE 0x10
829 +
830 +#define DMA_CTL_STATUS_APPEND_CRC 0x00000100
831 +#define DMA_CTL_STATUS_APPEND_BRCM_TAG 0x00000200
832 +#define DMA_CTL_STATUS_PRIO 0x00000C00 /* Prio for Tx */
833 +#define DMA_CTL_STATUS_WRAP 0x00001000 /* */
834 +#define DMA_CTL_STATUS_SOP 0x00002000 /* first buffer in packet */
835 +#define DMA_CTL_STATUS_EOP 0x00004000 /* last buffer in packet */
836 +#define DMA_CTL_STATUS_OWN 0x00008000 /* cleared by DMA, set by SW */
837 +#define DMA_CTL_LEN_DESC_BUFLENGTH 0x0fff0000
838 +#define DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT 16
839 +#define DMA_CTL_LEN_DESC_MULTICAST 0x40000000
840 +#define DMA_CTL_LEN_DESC_USEFPM 0x80000000
841 +
842 +#endif
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