git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From 3b48a7d925a757b3fa53c04baaf68bb8313c3ffb Mon Sep 17 00:00:00 2001
   2 From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
   3 Date: Thu, 14 Sep 2023 12:29:58 +0530
   4 Subject: [PATCH] arm64: dts: qcom: ipq8074: include the GPLL0 as clock
   5  provider for mailbox
   6
   7 While the kernel is booting up, APSS PLL will be running at 800MHz with
   8 GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
   9 configured to the rate based on the opp table and the source also will
  10 be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0,
  11 with this inclusion, CPU Freq correctly reports that CPU is running at
  12 800MHz rather than 24MHz.
  13
  14 Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
  15 Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
  16 ---
  17  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
  18  1 file changed, 2 insertions(+), 2 deletions(-)
  19
  20 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  21 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  22 @@ -682,8 +682,8 @@
  23                 apcs_glb: mailbox@b111000 {
  24                         compatible = "qcom,ipq8074-apcs-apps-global";
  25                         reg = <0x0b111000 0x1000>;
  26 -                       clocks = <&a53pll>, <&xo>;
  27 -                       clock-names = "pll", "xo";
  28 +                       clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
  29 +                       clock-names = "pll", "xo", "gpll0";
  30
  31                         #clock-cells = <1>;
  32                         #mbox-cells = <1>;