git.openwrt.org Git - openwrt/staging/ldir.git/blob

   1 From c91b7fb8fbb2e18ebb497e67f4252cec78e3a29b Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
   3 Date: Mon, 22 Jan 2024 08:35:55 +0300
   4 Subject: [PATCH 08/30] net: dsa: mt7530: improve comments regarding switch
   5  ports
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 There's no logic to numerically order the CPU ports. Just state the port
  11 number instead.
  12
  13 Remove the irrelevant PHY muxing information from
  14 mt7530_mac_port_get_caps(). Explain the supported MII modes instead.
  15
  16 Remove the out of place PHY muxing information from
  17 mt753x_phylink_mac_config(). The function is for MT7530, MT7531, and the
  18 switch on the MT7988 SoC but there's no PHY muxing on MT7531 or the switch
  19 on the MT7988 SoC.
  20
  21 These comments were gradually introduced with the commits below.
  22 commit ca366d6c889b ("net: dsa: mt7530: Convert to PHYLINK API")
  23 commit 38f790a80560 ("net: dsa: mt7530: Add support for port 5")
  24 commit 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding
  25 a new hardware")
  26 commit c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch")
  27
  28 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
  29 Acked-by: Daniel Golle <daniel@makrotopia.org>
  30 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  31 Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
  32 Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-4-042401f2b279@arinc9.com
  33 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  34 ---
  35  drivers/net/dsa/mt7530.c | 30 ++++++++++++++++++++----------
  36  1 file changed, 20 insertions(+), 10 deletions(-)
  37
  38 --- a/drivers/net/dsa/mt7530.c
  39 +++ b/drivers/net/dsa/mt7530.c
  40 @@ -2735,12 +2735,14 @@ static void mt7530_mac_port_get_caps(str
  41                                      struct phylink_config *config)
  42  {
  43         switch (port) {
  44 -       case 0 ... 4: /* Internal phy */
  45 +       /* Ports which are connected to switch PHYs. There is no MII pinout. */
  46 +       case 0 ... 4:
  47                 __set_bit(PHY_INTERFACE_MODE_GMII,
  48                           config->supported_interfaces);
  49                 break;
  50
  51 -       case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
  52 +       /* Port 5 supports rgmii with delays, mii, and gmii. */
  53 +       case 5:
  54                 phy_interface_set_rgmii(config->supported_interfaces);
  55                 __set_bit(PHY_INTERFACE_MODE_MII,
  56                           config->supported_interfaces);
  57 @@ -2748,7 +2750,8 @@ static void mt7530_mac_port_get_caps(str
  58                           config->supported_interfaces);
  59                 break;
  60
  61 -       case 6: /* 1st cpu port */
  62 +       /* Port 6 supports rgmii and trgmii. */
  63 +       case 6:
  64                 __set_bit(PHY_INTERFACE_MODE_RGMII,
  65                           config->supported_interfaces);
  66                 __set_bit(PHY_INTERFACE_MODE_TRGMII,
  67 @@ -2763,19 +2766,24 @@ static void mt7531_mac_port_get_caps(str
  68         struct mt7530_priv *priv = ds->priv;
  69
  70         switch (port) {
  71 -       case 0 ... 4: /* Internal phy */
  72 +       /* Ports which are connected to switch PHYs. There is no MII pinout. */
  73 +       case 0 ... 4:
  74                 __set_bit(PHY_INTERFACE_MODE_GMII,
  75                           config->supported_interfaces);
  76                 break;
  77
  78 -       case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
  79 +       /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on
  80 +        * MT7531AE.
  81 +        */
  82 +       case 5:
  83                 if (!priv->p5_sgmii) {
  84                         phy_interface_set_rgmii(config->supported_interfaces);
  85                         break;
  86                 }
  87                 fallthrough;
  88
  89 -       case 6: /* 1st cpu port supports sgmii/8023z only */
  90 +       /* Port 6 supports sgmii/802.3z. */
  91 +       case 6:
  92                 __set_bit(PHY_INTERFACE_MODE_SGMII,
  93                           config->supported_interfaces);
  94                 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
  95 @@ -2794,11 +2802,13 @@ static void mt7988_mac_port_get_caps(str
  96         phy_interface_zero(config->supported_interfaces);
  97
  98         switch (port) {
  99 -       case 0 ... 4: /* Internal phy */
 100 +       /* Ports which are connected to switch PHYs. There is no MII pinout. */
 101 +       case 0 ... 4:
 102                 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
 103                           config->supported_interfaces);
 104                 break;
 105
 106 +       /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */
 107         case 6:
 108                 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
 109                           config->supported_interfaces);
 110 @@ -2962,12 +2972,12 @@ mt753x_phylink_mac_config(struct dsa_swi
 111         u32 mcr_cur, mcr_new;
 112
 113         switch (port) {
 114 -       case 0 ... 4: /* Internal phy */
 115 +       case 0 ... 4:
 116                 if (state->interface != PHY_INTERFACE_MODE_GMII &&
 117                     state->interface != PHY_INTERFACE_MODE_INTERNAL)
 118                         goto unsupported;
 119                 break;
 120 -       case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
 121 +       case 5:
 122                 if (priv->p5_interface == state->interface)
 123                         break;
 124
 125 @@ -2977,7 +2987,7 @@ mt753x_phylink_mac_config(struct dsa_swi
 126                 if (priv->p5_intf_sel != P5_DISABLED)
 127                         priv->p5_interface = state->interface;
 128                 break;
 129 -       case 6: /* 1st cpu port */
 130 +       case 6:
 131                 if (priv->p6_interface == state->interface)
 132                         break;
 133