5a705974575bbf588d2e8b7606753ebf5d5dae45
[openwrt/staging/ynezz.git] /
1 From 4de7a5e35eff9216fa5e6b138b0ffa75e045e397 Mon Sep 17 00:00:00 2001
2 From: Xiaowei Bao <xiaowei.bao@nxp.com>
3 Date: Thu, 28 Feb 2019 14:09:01 +0800
4 Subject: [PATCH] arm64: dts: freescale: lx2160a: add pcie EP mode DT nodes
5
6 The LX2160A PCIe EP mode node.
7
8 Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
9 ---
10 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 56 ++++++++++++++++++++++++++
11 1 file changed, 56 insertions(+)
12
13 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
14 +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
15 @@ -932,6 +932,15 @@
16 status = "disabled";
17 };
18
19 + pcie_ep@3400000 {
20 + compatible = "fsl,lx2160a-pcie-ep";
21 + reg = <0x00 0x03400000 0x0 0x00100000
22 + 0x80 0x00000000 0x8 0x00000000>;
23 + reg-names = "regs", "addr_space";
24 + num-ob-windows = <256>;
25 + status = "disabled";
26 + };
27 +
28 pcie@3500000 {
29 compatible = "fsl,lx2160a-pcie";
30 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
31 @@ -959,6 +968,15 @@
32 status = "disabled";
33 };
34
35 + pcie_ep@3500000 {
36 + compatible = "fsl,lx2160a-pcie-ep";
37 + reg = <0x00 0x03500000 0x0 0x00100000
38 + 0x88 0x00000000 0x8 0x00000000>;
39 + reg-names = "regs", "addr_space";
40 + num-ob-windows = <256>;
41 + status = "disabled";
42 + };
43 +
44 pcie@3600000 {
45 compatible = "fsl,lx2160a-pcie";
46 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
47 @@ -986,6 +1004,16 @@
48 status = "disabled";
49 };
50
51 + pcie_ep@3600000 {
52 + compatible = "fsl,lx2160a-pcie-ep";
53 + reg = <0x00 0x03600000 0x0 0x00100000
54 + 0x90 0x00000000 0x8 0x00000000>;
55 + reg-names = "regs", "addr_space";
56 + num-ob-windows = <256>;
57 + max-functions = <2>;
58 + status = "disabled";
59 + };
60 +
61 pcie@3700000 {
62 compatible = "fsl,lx2160a-pcie";
63 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
64 @@ -1013,6 +1041,15 @@
65 status = "disabled";
66 };
67
68 + pcie_ep@3700000 {
69 + compatible = "fsl,lx2160a-pcie-ep";
70 + reg = <0x00 0x03700000 0x0 0x00100000
71 + 0x98 0x00000000 0x8 0x00000000>;
72 + reg-names = "regs", "addr_space";
73 + num-ob-windows = <256>;
74 + status = "disabled";
75 + };
76 +
77 pcie@3800000 {
78 compatible = "fsl,lx2160a-pcie";
79 reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
80 @@ -1040,6 +1077,16 @@
81 status = "disabled";
82 };
83
84 + pcie_ep@3800000 {
85 + compatible = "fsl,lx2160a-pcie-ep";
86 + reg = <0x00 0x03800000 0x0 0x00100000
87 + 0xa0 0x00000000 0x8 0x00000000>;
88 + reg-names = "regs", "addr_space";
89 + num-ob-windows = <256>;
90 + max-functions = <2>;
91 + status = "disabled";
92 + };
93 +
94 pcie@3900000 {
95 compatible = "fsl,lx2160a-pcie";
96 reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
97 @@ -1067,6 +1114,15 @@
98 status = "disabled";
99 };
100
101 + pcie_ep@3900000 {
102 + compatible = "fsl,lx2160a-pcie-ep";
103 + reg = <0x00 0x03900000 0x0 0x00100000
104 + 0xa8 0x00000000 0x8 0x00000000>;
105 + reg-names = "regs", "addr_space";
106 + num-ob-windows = <256>;
107 + status = "disabled";
108 + };
109 +
110 smmu: iommu@5000000 {
111 compatible = "arm,mmu-500";
112 reg = <0 0x5000000 0 0x800000>;