git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From b8714036be64c86a274ea49ba0066af0a81c6b98 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Thu, 26 Dec 2019 11:36:50 +0100
   4 Subject: [PATCH] drm/vc4: crtc: Deal with different number of pixel
   5  per clock
   6
   7 Some of the HDMI pixelvalves in vc5 output two pixels per clock cycle.
   8 Let's put the number of pixel output per clock cycle in the CRTC data and
   9 update the various calculations to reflect that.
  10
  11 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  12 ---
  13  drivers/gpu/drm/vc4/vc4_crtc.c | 17 ++++++++++-------
  14  drivers/gpu/drm/vc4/vc4_drv.h  |  3 +++
  15  2 files changed, 13 insertions(+), 7 deletions(-)
  16
  17 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  18 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  19 @@ -281,6 +281,7 @@ static void vc4_crtc_config_pv(struct dr
  20         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
  21                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
  22         u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
  23 +       u8 ppc = vc4_crtc->data->pixels_per_clock;
  24
  25         /* Reset the PV fifo. */
  26         CRTC_WRITE(PV_CONTROL, 0);
  27 @@ -288,17 +289,16 @@ static void vc4_crtc_config_pv(struct dr
  28         CRTC_WRITE(PV_CONTROL, 0);
  29
  30         CRTC_WRITE(PV_HORZA,
  31 -                  VC4_SET_FIELD((mode->htotal -
  32 -                                 mode->hsync_end) * pixel_rep,
  33 +                  VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
  34                                  PV_HORZA_HBP) |
  35 -                  VC4_SET_FIELD((mode->hsync_end -
  36 -                                 mode->hsync_start) * pixel_rep,
  37 +                  VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,
  38                                  PV_HORZA_HSYNC));
  39 +
  40         CRTC_WRITE(PV_HORZB,
  41 -                  VC4_SET_FIELD((mode->hsync_start -
  42 -                                 mode->hdisplay) * pixel_rep,
  43 +                  VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,
  44                                  PV_HORZB_HFP) |
  45 -                  VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
  46 +                  VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
  47 +                                PV_HORZB_HACTIVE));
  48
  49         CRTC_WRITE(PV_VERTA,
  50                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
  51 @@ -1038,6 +1038,7 @@ static const struct drm_crtc_helper_func
  52  static const struct vc4_crtc_data bcm2835_pv0_data = {
  53         .hvs_channel = 0,
  54         .debugfs_name = "crtc0_regs",
  55 +       .pixels_per_clock = 1,
  56         .encoder_types = {
  57                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
  58                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
  59 @@ -1047,6 +1048,7 @@ static const struct vc4_crtc_data bcm283
  60  static const struct vc4_crtc_data bcm2835_pv1_data = {
  61         .hvs_channel = 2,
  62         .debugfs_name = "crtc1_regs",
  63 +       .pixels_per_clock = 1,
  64         .encoder_types = {
  65                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
  66                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
  67 @@ -1056,6 +1058,7 @@ static const struct vc4_crtc_data bcm283
  68  static const struct vc4_crtc_data bcm2835_pv2_data = {
  69         .hvs_channel = 1,
  70         .debugfs_name = "crtc2_regs",
  71 +       .pixels_per_clock = 1,
  72         .encoder_types = {
  73                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
  74                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
  75 --- a/drivers/gpu/drm/vc4/vc4_drv.h
  76 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
  77 @@ -455,6 +455,9 @@ struct vc4_crtc_data {
  78         /* Which channel of the HVS this pixelvalve sources from. */
  79         int hvs_channel;
  80
  81 +       /* Number of pixels output per clock period */
  82 +       u8 pixels_per_clock;
  83 +
  84         enum vc4_encoder_type encoder_types[4];
  85         const char *debugfs_name;
  86  };