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1 From a1c9f7d1d24e90294f6a6755b137fcf306851e93 Mon Sep 17 00:00:00 2001
2 From: Daniel Golle <daniel@makrotopia.org>
3 Date: Tue, 25 Jul 2023 01:53:28 +0100
4 Subject: [PATCH 104/250] net: ethernet: mtk_eth_soc: convert clock bitmap to
5 u64
6
7 The to-be-added MT7988 SoC adds many new clocks which need to be
8 controlled by the Ethernet driver, which will result in their total
9 number exceeding 32.
10 Prepare by converting clock bitmaps into 64-bit types.
11
12 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
13 Link: https://lore.kernel.org/r/6960a39bb0078cf84d7642a9558e6a91c6cc9df3.1690246066.git.daniel@makrotopia.org
14 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
15 ---
16 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 96 +++++++++++----------
17 1 file changed, 49 insertions(+), 47 deletions(-)
18
19 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
20 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
21 @@ -666,54 +666,56 @@ enum mtk_clks_map {
22 MTK_CLK_MAX
23 };
24
25 -#define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
26 - BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \
27 - BIT(MTK_CLK_TRGPLL))
28 -#define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
29 - BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
30 - BIT(MTK_CLK_GP2) | \
31 - BIT(MTK_CLK_SGMII_TX_250M) | \
32 - BIT(MTK_CLK_SGMII_RX_250M) | \
33 - BIT(MTK_CLK_SGMII_CDR_REF) | \
34 - BIT(MTK_CLK_SGMII_CDR_FB) | \
35 - BIT(MTK_CLK_SGMII_CK) | \
36 - BIT(MTK_CLK_ETH2PLL))
37 +#define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
38 + BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
39 + BIT_ULL(MTK_CLK_TRGPLL))
40 +#define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
41 + BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
42 + BIT_ULL(MTK_CLK_GP2) | \
43 + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
44 + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
45 + BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
46 + BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
47 + BIT_ULL(MTK_CLK_SGMII_CK) | \
48 + BIT_ULL(MTK_CLK_ETH2PLL))
49 #define MT7621_CLKS_BITMAP (0)
50 #define MT7628_CLKS_BITMAP (0)
51 -#define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
52 - BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
53 - BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
54 - BIT(MTK_CLK_SGMII_TX_250M) | \
55 - BIT(MTK_CLK_SGMII_RX_250M) | \
56 - BIT(MTK_CLK_SGMII_CDR_REF) | \
57 - BIT(MTK_CLK_SGMII_CDR_FB) | \
58 - BIT(MTK_CLK_SGMII2_TX_250M) | \
59 - BIT(MTK_CLK_SGMII2_RX_250M) | \
60 - BIT(MTK_CLK_SGMII2_CDR_REF) | \
61 - BIT(MTK_CLK_SGMII2_CDR_FB) | \
62 - BIT(MTK_CLK_SGMII_CK) | \
63 - BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
64 -#define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
65 - BIT(MTK_CLK_WOCPU0) | \
66 - BIT(MTK_CLK_SGMII_TX_250M) | \
67 - BIT(MTK_CLK_SGMII_RX_250M) | \
68 - BIT(MTK_CLK_SGMII_CDR_REF) | \
69 - BIT(MTK_CLK_SGMII_CDR_FB) | \
70 - BIT(MTK_CLK_SGMII2_TX_250M) | \
71 - BIT(MTK_CLK_SGMII2_RX_250M) | \
72 - BIT(MTK_CLK_SGMII2_CDR_REF) | \
73 - BIT(MTK_CLK_SGMII2_CDR_FB) | \
74 - BIT(MTK_CLK_SGMII_CK))
75 -#define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
76 - BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
77 - BIT(MTK_CLK_SGMII_TX_250M) | \
78 - BIT(MTK_CLK_SGMII_RX_250M) | \
79 - BIT(MTK_CLK_SGMII_CDR_REF) | \
80 - BIT(MTK_CLK_SGMII_CDR_FB) | \
81 - BIT(MTK_CLK_SGMII2_TX_250M) | \
82 - BIT(MTK_CLK_SGMII2_RX_250M) | \
83 - BIT(MTK_CLK_SGMII2_CDR_REF) | \
84 - BIT(MTK_CLK_SGMII2_CDR_FB))
85 +#define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
86 + BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
87 + BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \
88 + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
89 + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
90 + BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
91 + BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
92 + BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
93 + BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
94 + BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
95 + BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
96 + BIT_ULL(MTK_CLK_SGMII_CK) | \
97 + BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP))
98 +#define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
99 + BIT_ULL(MTK_CLK_GP1) | \
100 + BIT_ULL(MTK_CLK_WOCPU0) | \
101 + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
102 + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
103 + BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
104 + BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
105 + BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
106 + BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
107 + BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
108 + BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
109 + BIT_ULL(MTK_CLK_SGMII_CK))
110 +#define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
111 + BIT_ULL(MTK_CLK_GP1) | \
112 + BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \
113 + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
114 + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
115 + BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
116 + BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
117 + BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
118 + BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
119 + BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
120 + BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
121
122 enum mtk_dev_state {
123 MTK_HW_INIT,
124 @@ -1046,7 +1048,7 @@ struct mtk_soc_data {
125 const struct mtk_reg_map *reg_map;
126 u32 ana_rgc3;
127 u64 caps;
128 - u32 required_clks;
129 + u64 required_clks;
130 bool required_pctl;
131 u8 offload_version;
132 u8 hash_offset;
Staging tree of Matthias Schiffer