git.openwrt.org Git - openwrt/staging/wigyori.git/blob

   1 From fa14c96eab3ec5b7cb44b06c0a54a851849a9810 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
   3 Date: Wed, 20 Mar 2024 23:45:30 +0300
   4 Subject: [PATCH 29/30] net: dsa: mt7530: fix improper frames on all 25MHz and
   5  40MHz XTAL MT7530
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   9
  10 The MT7530 switch after reset initialises with a core clock frequency that
  11 works with a 25MHz XTAL connected to it. For 40MHz XTAL, the core clock
  12 frequency must be set to 500MHz.
  13
  14 The mt7530_pll_setup() function is responsible of setting the core clock
  15 frequency. Currently, it runs on MT7530 with 25MHz and 40MHz XTAL. This
  16 causes MT7530 switch with 25MHz XTAL to egress and ingress frames
  17 improperly.
  18
  19 Introduce a check to run it only on MT7530 with 40MHz XTAL.
  20
  21 The core clock frequency is set by writing to a switch PHY's register.
  22 Access to the PHY's register is done via the MDIO bus the switch is also
  23 on. Therefore, it works only when the switch makes switch PHYs listen on
  24 the MDIO bus the switch is on. This is controlled either by the state of
  25 the ESW_P1_LED_1 pin after reset deassertion or modifying bit 5 of the
  26 modifiable trap register.
  27
  28 When ESW_P1_LED_1 is pulled high, PHY indirect access is used. That means
  29 accessing PHY registers via the PHY indirect access control register of the
  30 switch.
  31
  32 When ESW_P1_LED_1 is pulled low, PHY direct access is used. That means
  33 accessing PHY registers via the MDIO bus the switch is on.
  34
  35 For MT7530 switch with 40MHz XTAL on a board with ESW_P1_LED_1 pulled high,
  36 the core clock frequency won't be set to 500MHz, causing the switch to
  37 egress and ingress frames improperly.
  38
  39 Run mt7530_pll_setup() after PHY direct access is set on the modifiable
  40 trap register.
  41
  42 With these two changes, all MT7530 switches with 25MHz and 40MHz, and
  43 P1_LED_1 pulled high or low, will egress and ingress frames properly.
  44
  45 Link: https://github.com/BPI-SINOVOIP/BPI-R2-bsp/blob/4a5dd143f2172ec97a2872fa29c7c4cd520f45b5/linux-mt/drivers/net/ethernet/mediatek/gsw_mt7623.c#L1039
  46 Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
  47 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
  48 Link: https://lore.kernel.org/r/20240320-for-net-mt7530-fix-25mhz-xtal-with-direct-phy-access-v1-1-d92f605f1160@arinc9.com
  49 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  50 ---
  51  drivers/net/dsa/mt7530.c | 5 +++--
  52  1 file changed, 3 insertions(+), 2 deletions(-)
  53
  54 --- a/drivers/net/dsa/mt7530.c
  55 +++ b/drivers/net/dsa/mt7530.c
  56 @@ -2274,8 +2274,6 @@ mt7530_setup(struct dsa_switch *ds)
  57                      SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
  58                      SYS_CTRL_REG_RST);
  59
  60 -       mt7530_pll_setup(priv);
  61 -
  62         /* Lower Tx driving for TRGMII path */
  63         for (i = 0; i < NUM_TRGMII_CTRL; i++)
  64                 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
  65 @@ -2291,6 +2289,9 @@ mt7530_setup(struct dsa_switch *ds)
  66         val |= MHWTRAP_MANUAL;
  67         mt7530_write(priv, MT7530_MHWTRAP, val);
  68
  69 +       if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
  70 +               mt7530_pll_setup(priv);
  71 +
  72         mt753x_trap_frames(priv);
  73
  74         /* Enable and reset MIB counters */