git.openwrt.org Git - openwrt/staging/wigyori.git/blob

   1 From 1d3e170344dff2cef8827db6c09909b78cbc11d7 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
   3 Date: Tue, 30 Nov 2021 18:29:05 +0100
   4 Subject: [PATCH] PCI: aardvark: Add support for DEVCAP2, DEVCTL2, LNKCAP2 and
   5  LNKCTL2 registers on emulated bridge
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 PCI aardvark hardware supports access to DEVCAP2, DEVCTL2, LNKCAP2 and
  11 LNKCTL2 configuration registers of PCIe core via PCIE_CORE_PCIEXP_CAP.
  12 Export them via emulated software root bridge.
  13
  14 Link: https://lore.kernel.org/r/20211130172913.9727-4-kabel@kernel.org
  15 Signed-off-by: Pali Rohár <pali@kernel.org>
  16 Signed-off-by: Marek Behún <kabel@kernel.org>
  17 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  18 ---
  19  drivers/pci/controller/pci-aardvark.c | 15 +++++++++++----
  20  1 file changed, 11 insertions(+), 4 deletions(-)
  21
  22 diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
  23 index c5300d49807a..25af189a1052 100644
  24 --- a/drivers/pci/controller/pci-aardvark.c
  25 +++ b/drivers/pci/controller/pci-aardvark.c
  26 @@ -884,8 +884,13 @@ advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
  27         case PCI_CAP_LIST_ID:
  28         case PCI_EXP_DEVCAP:
  29         case PCI_EXP_DEVCTL:
  30 +       case PCI_EXP_DEVCAP2:
  31 +       case PCI_EXP_DEVCTL2:
  32 +       case PCI_EXP_LNKCAP2:
  33 +       case PCI_EXP_LNKCTL2:
  34                 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
  35                 return PCI_BRIDGE_EMUL_HANDLED;
  36 +
  37         default:
  38                 return PCI_BRIDGE_EMUL_NOT_HANDLED;
  39         }
  40 @@ -899,10 +904,6 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
  41         struct advk_pcie *pcie = bridge->data;
  42
  43         switch (reg) {
  44 -       case PCI_EXP_DEVCTL:
  45 -               advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
  46 -               break;
  47 -
  48         case PCI_EXP_LNKCTL:
  49                 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
  50                 if (new & PCI_EXP_LNKCTL_RL)
  51 @@ -924,6 +925,12 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
  52                 advk_writel(pcie, new, PCIE_ISR0_REG);
  53                 break;
  54
  55 +       case PCI_EXP_DEVCTL:
  56 +       case PCI_EXP_DEVCTL2:
  57 +       case PCI_EXP_LNKCTL2:
  58 +               advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
  59 +               break;
  60 +
  61         default:
  62                 break;
  63         }
  64 --
  65 2.34.1
  66